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Advisory November 1998
T7234, T7237, and T7256 Compliance with the New ETSI PSD Requirement
(Refer to the T7234, T7237, and T7256 ISDN transceiver data sheets.)
Telecommunication Standard
The European Telecommunications Standards Institute (ETSI) has identified a change in the requirement of the power spectral density (PSD) for Basic Rate Interface ISDN. Section A.12.4, Power Spectral Density, of ETSI TS080 states the following:
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The upper boundary of the power spectral density of the transmitted signal shall be as shown in Figure 1, below. Measurements to verify compliance with this requirement are to use a noise power bandwidth of 1.0 kHz. Systems deployed before January 1, 2000 do not have to meet this PSD requirement but shall meet the PSD requirements as defined in ETR 080 edition 2. It is, however, expected that these systems will also meet the PSD requirements of TS080 edition 3. Some narrowband violations could occur and should be tolerated.
s s
-20 -30 -40 -50 PSD (dBm/Hz) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.001 0.010
0.050
1.000 0.315
30.000 5.000
0.100 f (MHz)
1.000
10.000
100.000
5-7388F
Figure 1. Upper Boundary of Power Spectral Density from NT1 and LT
The existing SCNT1 family (T7234A, T7237A, and T7256A) of U-interface transceivers fully comply with this standard. Conformance to the above requirement has been fully verified, and test reports are available upon request.
For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1998 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A.
November 1998 AY99-004ISDN (Must accompany DS97-410ISDN, DS97-411ISDN, DS97-412ISDN, and AY98-025ISDN)
Advisory July 1998
T7234, T7237, and T7256 Data Sheet Advisory
(Refer to the T7234, T7237, and T7256 ISDN transceiver data sheets.) The Technology and Telecommunications Standard sections below denote the differences between the T7234, T7237, and T7256 and the T7234A, T7237A, and T7256A.
Technology
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The T-7234- - -ML, T-7237- - -ML, and T-7256- - -ML2 are 0.9 m CMOS technology devices. The T-7234A- -ML, T-7237A- -ML, and T-7256A- -ML are 0.6 m CMOS technology devices.
Telecommunication Standard
In 1996, the European Telecommunications Standards Institute (ETSI) added a microinterruption immunity requirement to ETR 080 (Sections 5.4.5 and 6.2.5). Section 5.4.5 in ETSI ETR 080 states the following:
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A microinterruption is a temporary line interruption due to external mechanical activity on the copper wires constituting the transmission path. The effect of a microinterruption on the transmission system can be a failure of the digital transmission link. The objective of this requirement is that the presence of a microinterruption of specified maximum length shall not deactivate the system, and the system shall activate if it has deactivated due to longer interruption.
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Section 6.2.5 in ETSI ETR 080 states that:
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A system shall tolerate a microinterruption up to t = 5 ms, when simulated with a repetition interval of t = 5 ms.
The SCNT1 family of U-interface transceivers was upgraded to fully comply with this standard. The devices have been given an A suffix (T7234A, T7237A, and T7256A). A proposal was added to the Living List (which is intended to collect issues and observations for a possible future update of ETSI ETR 080) to change the value of the microinterruption from 5 ms to 10 ms. The current SCNT1 family of U-interface transceivers (T7234A/T7237A/T7256A) from Lucent Technologies Microelectronics Group meets and exceeds this new requirement. The above change to the SCNT1 family of transceivers has been fully verified, and test reports are available upon request.
T7234, T7237, and T7256 Data Sheet Advisory
Advisory July 1998
Application Circuit
Please change the value of capacitor C15 from 0.1 F to 1.0 F in Figure 11 of the T7234 data sheet, Figure 17 of the T7237 data sheet, and Figure 20 of the T7256 data sheet. The following schematic shows the correct value (1.0 F) for C15.
MLT CIRCUIT
C15 1.0 F R11 137
(PLACE THIS CAPACITOR AS CLOSE AS POSSIBLE TO THE LH1465) LH1465AB 8 1 TC PR+ 7 2 RS T U3 6 3 PD R 5 4 COM PR- R14 1.1 k 2W
+5 V R10 10 k 8 6 5 R9
R8 17.8 k SCNT1 OPTOIN PIN
U2
R12 137 2 3 CA 1.0 F ZD
R15 1.1 k 2W RING TIP
7
HCPL-0701
2.2 M
FOR NORTH AMERICAN APPLICATIONS ONLY
5-7034(C)
Figure 1. MLT Circuit Showing New Placement of Zener Diode (ZD) and Capacitor (CA) In the ILOSS mode (refer to ANSI T1.601 1992, Section 6.5.2), the NT generates a scrambled, framed, 2B1Q signal such as SN1 and SN2. When the ILOSS mode is applied to circuits with the LH1465, it was observed that for some short loop lengths, the NT, once in the ILOSS mode, would not respond to further maintenance pulses until the ILOSS timer expired. It was discovered that there is some portion of the transmitted 2B1Q signal from the NT that passes through the LH1465 to the optoisolator. This causes the optoisolator to report incorrect dial pulses at its output, and thus prevent the NT from properly exiting the ILOSS mode. To correct this situation, the dropout voltage (voltage at the Tip/Ring needed to turn on the optoisolator) of the optoisolator driver on the LH1465 is raised using the 3.6 V zener diode ZD (for example, Motorola* MMSZ4685T1). Capacitor CA is a 1.0 F 10% tantalum chip capacitor, with a voltage rating of at least 16 V. CA is added to provide a level of filtering for the transition points (turn-on or turn-off) of the optoisolator input voltage, which increases the robustness of the circuit.
* Motorola is a registered trademark of Motorola Inc.
For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 . JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell), FRANCE: (33) 1 48 83 68 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1998 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A.
July 1998 AY98-025ISDN (Replaces AY98-020ISDN) (Must accompany DS97-410ISDN, DS97-411ISDN, and DS97-412ISDN)
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Features
s
Description
The Lucent Technologies Microelectronics Group T7234 Single-Chip NT1 (SCNT1) Transceiver integrated circuit provides data (2B+D) and control information conversion between 2-wire (U-interface) and 4-wire (S/T-interface) digital subscriber loops on the integrated services digital network (ISDN). The T7234 conforms to the ANSI T1.601 standard and ETSI ETR 080 technical report for the U-interface and the ITU-T I.430 recommendation, ANSI T1.605 standard, and ETSI ETS 300 012 for the S/T-interface. The single +5 V CMOS device is packaged in a 44-pin plastic leaded chip carrier (PLCC).
U- to S/T-interface conversion for ISDN basic rate (2B+D) systems -- Integrated U- and S/T-interfaces -- Operates in stand-alone mode to provide U- and S/T-interface activation, control, and maintenance functions -- Automatic embedded operations channel (eoc) processing for ANSI T1.601 systems -- Low power consumption supporting line-powered NT1 (See Table 15 on page 49, Question and Answers section, #47 for detailed power consumption information) -- Idle-mode support (35 mW typical) -- Board-level testability support U-interface -- Conforms to ANSI T1.601 standard and ETSI ETR 080 technical report -- 2B1Q four-level line code -- Automatic ANSI maintenance functions (quiet mode and insertion loss mode plus the MLT function as an option for North America) S/T-interface -- Conforms to ANSI T1.605 standard, ITU-T I.430 recommendation, and ETSI ETS 300 012 for NT operation Other -- Single +5 V (5%) supply -- -40 C to +85 C -- 44-pin PLCC
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s
s
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Table of Contents
Contents Page
Features ....................................................................................................................................................................1 Description ................................................................................................................................................................1 Pin Information ..........................................................................................................................................................4 Functional Overview ..................................................................................................................................................8 U-Interface Frame Structure ......................................................................................................................................8 Bit Assignments .................................................................................................................................................9 S/T-Interface Frame Structure..................................................................................................................................10 U-Interface Description............................................................................................................................................12 S/T-Interface Description .........................................................................................................................................13 Loopbacks ...............................................................................................................................................................14 STLED Description ..................................................................................................................................................15 eoc State Machine Description................................................................................................................................17 ANSI Maintenance Control Description ...........................................................................................................17 Board-Level Testing .........................................................................................................................................17 Application Briefs.....................................................................................................................................................18 T7234 Reference Circuit ..................................................................................................................................18 Absolute Maximum Ratings.....................................................................................................................................24 Handling Precautions ..............................................................................................................................................24 Recommended Operating Conditions .....................................................................................................................24 Electrical Characteristics .........................................................................................................................................25 Power Consumption.........................................................................................................................................25 Pin Electrical Characteristics ...........................................................................................................................25 S/T-Interface Receiver Common-Mode Rejection............................................................................................26 Crystal Characteristics.....................................................................................................................................26 Timing Characteristics .............................................................................................................................................27 Switching Test Input/Output Waveform ............................................................................................................27 Propagation Delay ...........................................................................................................................................27 Outline Diagram.......................................................................................................................................................28 44-Pin PLCC....................................................................................................................................................28 Ordering Information................................................................................................................................................28 Questions and Answers...........................................................................................................................................29 Introduction ......................................................................................................................................................29 U-Interface .......................................................................................................................................................29 S/T-Interface.....................................................................................................................................................36 Miscellaneous ..................................................................................................................................................47 Glossary ..................................................................................................................................................................51 Standards Documentation .......................................................................................................................................55
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Table of Contents (continued)
Figures Page
Figure 1. Block Diagram ......................................................................................................................................... 4 Figure 2. Pin Diagram............................................................................................................................................. 4 Figure 3. U-Interface Frame and Superframe ........................................................................................................ 8 Figure 4. U-Interface Superframe Bit Groups......................................................................................................... 9 Figure 5. Frame Structures of NT and TE Frames ............................................................................................... 10 Figure 6. Details of NT and TE Frames................................................................................................................ 11 Figure 7. U-Interface Quat Example..................................................................................................................... 12 Figure 8. S/T-Interface ASI Example.................................................................................................................... 13 Figure 9. Location of the Loopback Configurations (Reference ITU-T I.430 Appendix I)..................................... 14 Figure 10. STLED Control Flow Diagram ............................................................................................................. 16 Figure 11. T7234 Stand-Alone Reference Circuit-A ............................................................................................. 19 Figure 12. T7234 Stand-Alone Reference Circuit-B ............................................................................................. 20 Figure 13. RESET Timing Diagram ...................................................................................................................... 27 Figure 14. Switching Test Waveform.................................................................................................................... 27 Figure 15. Transceiver Impedance Limits ............................................................................................................ 31 Figure 16. Receiver Bias ...................................................................................................................................... 38 Figure 17. T7234 S/T Line Interface Scheme....................................................................................................... 42 Figure 18. T7903 S/T Line Interface Scheme....................................................................................................... 42 Figure 19. T7250C S/T Line Interface Scheme .................................................................................................... 43 Figure 20. T7903 to T7234 Direct-Connect Scheme............................................................................................ 44 Figure 21. T7250C to T7234 Direct-Connect Scheme ......................................................................................... 44 Figure 22. T7903 to T7234 Direct-Connect Scheme with External S/T-Interface ................................................ 45 Figure 23. T7250C to T7234 Direct-Connect Scheme with External S/T-Interface.............................................. 46
Tables
Page
Table 1. Pin Descriptions........................................................................................................................................ 5 Table 2. U-Interface Bit Assignment ...................................................................................................................... 9 Table 3. Line Transmission Code......................................................................................................................... 13 Table 4. STLED States......................................................................................................................................... 15 Table 5. T7234 Reference Schematic Parts List .................................................................................................. 21 Table 6. Line-Side Resistor Requirements........................................................................................................... 23 Table 7. Power Consumption ............................................................................................................................... 25 Table 8. Digital dc Characteristics (Over Operating Ranges)............................................................................... 25 Table 9. S/T-Interface Receiver Common-Mode Rejection.................................................................................. 26 Table 10. Fundamental Mode Crystal Characteristics.......................................................................................... 26 Table 11. Internal PLL Characteristics ................................................................................................................. 26 Table 12. RESET Timing...................................................................................................................................... 27 Table 13. Power Dissipation Variation.................................................................................................................. 48 Table 14. Power Dissipation of CKOUT ............................................................................................................... 48 Table 15. Power Consumption ............................................................................................................................. 49
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Description (continued)
4-WIRE S/T-INTERFACE
eoc STATE MACHINE 2-WIRE 2B1Q U-INTERFACE CONTROL FLOW STATE MACHINE U TRANSCEIVER
S/TTRANSCEIVER
15.360 MHz ANSI MAINTENANCE DECODER CRYSTAL OSC.
5-2292.c (C)
Figure 1. Block Diagram
Pin Information
VDDD SYN8K/LBIND
OPTOIN GNDD
ILOSS
RESET VDDA
STLED
HIGHZ
6
5
4
3
2
1
44 43 42 41 40 39 38 37 36
FTE PS2E PS1E GNDD ACTMODE SYN8K_CTL VDDD NC AUTOACT GNDD NC
GNDA
GNDA VDDA SDINP SDINN HP LON GNDA VDDA LOP HN VRN VRP
35 34 33 32 31 30
7 8 9 10 11 12 13 14 15 16 17
T7234
29 18 19 20 21 22 23 24 25 26 27 28
X1
TNR TPR GNDA
RNR
RPR
Note: Pin labels shown in bold (pins 11, 12, and 15) represent chip configuration controls that are sampled on the rising edge of RESET (see Table 1, Pin Descriptions).
5-2296.c (C)
Figure 2. Pin Diagram
4
VRCM
GNDO
VDDO
X2 VDDA
Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Pin Information (continued)
Table 1. Pin Descriptions Pin 1, 10, 16 2 Symbol GNDD OPTOIN Type* Name/Function -- Digital Ground. Ground leads for digital circuitry. Iu Optoisolator Input. Pin accepts CMOS logic level maintenance pulse streams. These pulse streams typically are generated by an optoisolator that is monitoring the U loop. Pulse patterns on this pin are digitally filtered for 20 ms before being considered valid and are then decoded and interpreted using the ANSI maintenance state machine requirements. If the OPTOIN pin is being used for implementing maintenance functions, the ILOSS pin should not be used (i.e., it should be held high). An internal 100 k pull-up resistor is on this pin. For applications outside of North America, leave this pin unconnected. Status LED Driver. Output pin for driving an LED (source/sink 4.0 mA) that indicates the device status. The four defined states are low, high, 1 Hz flashing, and 8 Hz flashing (flashing occurs at 50% duty cycle). See the STLED Description section for a detailed explanation of these states. Also, this pin indicates device sanity upon power-on/RESET, as follows:
s
3
STLED
O
If AUTOACT = 0 (pin 15) after a device RESET, STLED will toggle at an 8 Hz rate for at least 0.5 s, signifying an activation attempt. If the activation attempt succeeds, it will continue to flash per the normal start-up sequence (see STLED Description section).
4
SYN8K/LBIND
O
5, 13 6
VDDD ILOSS
-- Iu
7
FTE
Iu
If AUTOACT = 1 (pin 15) after a device RESET, STLED will go low for 1 s (flash of life), indicating that the device is operational, and no activation attempt will be made. Synchronous 8 kHz Clock or Loopback Indicator. Pin function is selected via SYN8K_CTL (pin 12) state at the end of external RESET. As SYN8K (SYN8K_CTL = 0), this pin can be used as a reference clock or for synchronization in device performance testing (i.e., it reflects the recovered timing from the U-interface). SYN8K is always present, even when the chip is in its low-power (deactivated) mode. As LBIND (SYN8K_CTL = 1), this pin indicates a 2B+D loopback: 0--No loopback. 1--eoc requested 2B+D loopback in progress. Digital Power. 5 V 5% power supply pins for digital circuitry. Insertion Loss Test Control (Active-Low). The ILOSS pin is used to control SN1 tone transmission for maintenance. The OPTOIN and ILOSS pins should not be used at the same time (i.e., OPTOIN should be held high when ILOSS is active). This pin would typically be used if an external ANSI maintenance decoder is being used, in which case the decoder output drives the ILOSS pin. Internal 100 k pull-up resistor on this pin. 0--U transmitter sends SN1 tone continuously. 1--No effect on device operation. Fixed/Adaptive Timing Mode Select. Selects S/T-interface timing recovery mode: 0--Fixed timing recovery mode. 1--Adaptive timing recovery mode.
s
* Iu = input with internal pull-up.
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin 8 Symbol PS2E Type* Id Name/Function Power Status #2. This is an input for the PS2 bit in transmit U-interface data stream. If the PS2E functionality is not used, this input must be pulled up externally with a 10 k or less resistor to set the U-interface PS2 bit to the inactive state. An internal 100 k pull-down resistor is on this pin. Power Status #1. This is an input for the PS2 bit in transmit U-interface data stream. If the PS1E functionality is not used, this input must be pulled up externally with a 10 k or less resistor to set the U-interface PS1 bit to the inactive state. An internal 100 k pull-down resistor is on this pin. ACT Bit Mode. 0--act = 0 during loopback 2 (per ANSI T1.601). The data received at the NT is looped back towards the LT as soon as the 2B+D loopback is enabled. 1--act = 1 during loopback 2 after INFO 3 is recognized at the S/T-interface (per ETR 080). The data received by the NT is not looped back towards the LT until after ACT = 1 is received from the LT. Prior to this time, 2B+D data toward the LT is all 1s. Synchronous 8 kHz Clock Control. If pin is held low during an external RESET, the SYN8K/LBIND pin performs the SYN8K function. If held high during an external RESET, the pin performs the LBIND function. An internal 100 k pull-down resistor is on this pin. No Connect. Automatic Activation. If this pin is held low during an external RESET, the AUTOACT bit is written to 0, creating an activation attempt. If pin is held high during external RESET, no activation is attempted. An internal 100 k pull-down resistor is on this pin. No Connect. Crystal Oscillator Ground. Ground lead for crystal oscillator. Crystal Oscillator Power. Power supply lead for crystal oscillator. Crystal #1. Crystal connection #1 for 15.36 MHz oscillator. Crystal #2. Crystal connection #2 for 15.36 MHz oscillator. Analog Power. 5 V 5% power supply leads for analog circuitry. Transmit Negative Rail for S/T-Interface. Negative output of S/T-interface analog transmitter. Connect to transformer through a 121 1% resistor. Transmit Positive Rail for S/T-Interface. Positive output of S/T-interface analog transmitter. Connect to transformer through a 121 1% resistor.
9
PS1E
Id
11
ACTMODE
Iu
12
SYN8K_CTL
Id
14 15
NC AUTOACT
-- Id
17 18 19 20 21 22, 33, 39, 42 23 24
NC GNDO VDDO X1 X2 VDDA TNR TPR
-- -- -- O I -- O O
* Iu = input with internal pull-up; Id = input with internal pull-down.
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Pin Information (continued)
Table 1. Pin Description (continued) Pin 25, 34, 40, 41 26 27 28 29 30 31 32 35 36 37 38 43 Symbol GNDA RNR RPR VRCM VRP VRN HN LOP LON HP SDINN SDINP RESET Type* Name/Function -- Analog Ground. Ground leads for analog circuitry. I I -- -- -- I O O I I I Id Receive Negative Rail for S/T-Interface. Negative input of S/T-interface analog receiver. Connect to transformer through a 10 k 10% resistor. Receive Positive Rail for S/T-Interface. Positive input of S/T-interface analog receiver. Connect to transformer through a 10 k 10% resistor. Common-Mode Voltage Reference for U-Interface Circuits. Connect a 0.1 F 20% capacitor to GNDA (as close to the device pins as possible). Positive Voltage Reference for U-Interface Circuits. Connect a 0.1 F 20% capacitor to GNDA (as close to the device pins as possible). Negative Voltage Reference for U-Interface Circuits. Connect a 0.1 F 20% capacitor to GNDA (as close to the device pins as possible). Hybrid Negative Input for U-Interface. Connect directly to negative side of U-interface transformer. Line Driver Positive Output for U-Interface. Connect to the U-interface transformer through a 16.9 1% resistor. Line Driver Negative Output for U-Interface. Connect to the U-interface transformer through a 16.9 1% resistor. Hybrid Positive Input for U-Interface. Connect directly to positive side of U-interface transformer. Sigma-Delta A/D Negative Input for U-Interface. Connect via an 820 pF 5% capacitor to SDINP. Sigma-Delta A/D Positive Input for U-Interface. Connect via an 820 pF 5% capacitor to SDINN. Reset (Active-Low). Asynchronous Schmitt trigger input. Reset halts data transmission, clears adaptive filter coefficients, resets the U-transceiver timing recovery circuitry, resets the S/T-interface transceiver, and sets all microprocessor register bits to their default state. During reset, the U-interface transmitter produces 0 V and the output impedance is 135 at tip and ring. The RESET pin can be used to implement quiet mode maintenance testing (refer to pin 2 for more description). The states of ACTMODE, SYN8K_CTL, and AUTOACT are read upon exiting reset state (see corresponding pin descriptions). An internal 100 k pull-down resistor is on this pin. RESET must be held low for 1.5 ms after power-on. Device is fully functional after an additional 1 ms. High-Impedance Control (Active-Low). Control of the high-impedance function. An internal 100 k pull-up resistor is on this pin. Note: This pin does not 3-state the analog outputs. 0--All digital outputs enter high-impedance state. 1--No effect on device operation.
44
HIGHZ
Iu
* Iu = input with internal pull-up; Id = input with internal pull-down.
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Functional Overview
The T7234 device provides two interfaces for information transfer: the U-interface, the S/T-interface. The ANSI maintenance controller can operate in fully automatic or in fully manual mode. In automatic mode, the device decodes and responds to maintenance states according to the ANSI requirements. In manual mode, the device is controlled by an external maintenance decoder that drives the RESET and ILOSS pins to implement the required maintenance states. When the T7234 is powered on and there is no activity on the S/T- or U-interfaces (i.e., no pending activation request), it automatically enters a low-power IDLE mode in which it consumes an average of 35 mW. This mode is exited automatically when an activation or U maintenance request occurs from the S/T- or U-interfaces. The T7234 provides a board-level test capability that allows functional verification. Finally, an LED driver output indicates the status of the device during operation.
U-Interface Frame Structure
Data is transmitted over the U-interface in 240-bit groups called U frames. Each U frame consists of an 18-bit synchronization word or inverted synchronization word (SW or ISW), 12 blocks of 2B+D data (216 bits), and six overhead bits (M bits). A U-interface superframe consists of eight U frames grouped together. The beginning of a U superframe is indicated by the inverted sync word (ISW). The six overhead bits (M1-- M6) from each of the eight U frames, when taken together, form the 48 M bits. Figure 3 shows how U frames, superframes, and M bits are arranged. Of the 48 M bits, 24 bits form the embedded operations channel (eoc) for sending messages from the LT to the NT and responses from the NT to the LT. There are two eoc messages per superframe with 12 bits per eoc message (eoc1 and eoc2). Another 12 bits serve as Uinterface control and status bits (UCS). The last 12 bits form the cyclic redundancy check (CRC) which is calculated over the 2B+D data and the M4 bits of the previous superframe. Figure 4 and Table 2 show the different groups of bits in the superframe.
U-FRAME SPAN = 1.5 ms ISW[18] (2B+D) x 12 [216 bits] M[6]
U-SUPERFRAME SPAN = 12 ms U1 U2 U3 U4 U5 U6 U7 U8
U-INTERFACE M BITS [48]
5-2476 (C)
Figure 3. U-Interface Frame and Superframe
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
U-Interface Frame Structure (continued)
Bit # Frame # 1 2 3 4 5 6 7 8 1--18 Sync ISW 19--234 12(2B+D) 235 M1 236 M2 eoc1 237 M3 238 M4 239 M5 240 M6
CONTROL & STATUS (UCS)
SW
2B+D eoc2 crc
Figure 4. U-Interface Superframe Bit Groups
Bit Assignments
Table 2. U-Interface Bit Assignment Bit # Frame # 1 2 3 4 5 6 7 8 1--18 Sync ISW SW SW SW SW SW SW SW 19--234 12(2B+D) 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D 235 M1 eoca1 eocdm eoci3 eoci6 eoca1 eocdm eoci3 eoci6 236 M2 eoca2 eoci1 eoci4 eoci7 eoca2 eoci1 eoci4 eoci7 237 M3 eoca3 eoci2 eoci5 eoci8 eoca3 eoci2 eoci5 eoci8 238 M4 act dea (ps1)* R3, 4 (ps2)* R4, 4 (ntm)* R5, 4 (cso)* R6, 4 uoa (sai)* aib (nib)* 239 M5 R1, 5 R2, 5 crc1 crc3 crc5 crc7 crc9 crc11 240 M6 R1, 6 febe crc2 crc4 crc6 crc8 crc10 crc12
* LT(NT). Values in parentheses () indicate meaning at the NT. cso is fixed at 0 by the device to indicate both cold and warm start capability. nib is fixed at 1 by the device to indicate the link is normal.
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
S/T-Interface Frame Structure
The S/T-interface transfers its subscriber line 2B+D information as a 192 kbits/s full-duplex signal grouped into frames of 48 bits with a period of 250 s, as specified in the ITU-T I.430/ANSI T1.605 standard. Thirty-six of the 48 bits sent in each direction convey user information (two 8-bit occurrences of each of the two B channels, and four D-channel bits). The remaining 12 bits per frame are used for framing, control, dc balance, and maintenance. The frame structures are shown in each direction in Figure 5. In the bit stream transmitted from the terminal endpoint (TE) to the network termination (NT), 4 bits are used for framing (F and FA, each with a dc balancing bit L), eight additional L bits are used to balance the 32 Bchannel bits, and 4 bits are D-channel bits. For the NT-to-TE transmission, 4 bits (F with dc balancing bit L, FA, and N) are used for framing, one M bit marks the start of a 20-frame multiframe, four E bits
form an echo channel for retransmission of the D-channel bits received from the TE, one additional L bit is used to balance the contents of the entire frame, and 1 bit (A) is set to one when bit synchronization is achieved between TE and NT as part of the INFO 4 state. One S bit is used for transmitting S-subchannel messages in an NT-to-TE multiframe. The framing procedure uses bipolar line-code violations to establish synchronization. Since the last binary 0 of any frame is a positive pulse and the F bit is also defined to be a positive pulse (see Figure 6), the first bit of each frame represents a coding violation. In addition, the second bit of each frame, a balance bit, is a negative pulse, and the next binary 0 in the frame is forced to be negative, causing another violation. Both bipolar violations allow framing and provide dc balance. All other pulses follow the alternating convention.
ONE FRAME = 48 bits IN 250 s NT-TOTE FRAME
F
L
EIGHT B1 BITS
E D A FA N
EIGHT B2 BITS
EDM
EIGHT B1 BITS
EDS
EIGHT B2 BITS
ED
L
TE-TONT FRAME
F
L
EIGHT B1 BITS
LD
L FA L
EIGHT B2 BITS
L
DL
EIGHT B1 BITS
L
DL
EIGHT B2 BITS
L
D
L
BANDWIDTH = 192 kbits/s
5-2479 (C)
Figure 5. Frame Structures of NT and TE Frames
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
S/T-Interface Frame Structure (continued)
In the TE-to-NT direction, in at least four of five frames, this second violation occurs within 13 bits of the F bit. If this coding algorithm is not maintained, the receiver loses synchronization, but the T7234 continues transmitting. Multiframing is not supported in the T7234.
TIME LF 48 1 L B1 B1 2 3 4 B1 B1 E D A FA N B2 B2 9 10 11 12 13 14 15 16 17 48 bits IN 250 s B2 E D M B1 B1 23 24 25 26 27 28 B1 E D S B2 B2 B2 E DL F L
34 35 36 37 38 39
45 46 47 48 1
(NT TO TE)
FA/N BIT PAIR INVERT TO FLAG Q-BIT TRANSMISSION MULTIFRAME SYNC BIT (OPTIONAL, ONCE IN 20 FRAMES)
+0 1 -0
DL
F 2
B1 3 4
B1 L
D L FA L B2 B2
B2 L
D
L B1 B1
B1 L
D
L B2 B2
B2 L
D
L
48 1
10 11 12 13 14 15 16 17
23 24 25 26 27 28
34 35 36 37 38 39
45 46 47 48
(TE TO NT)
2-bit OFFSET Q-BIT OPTION (EVERY 5TH FRAME)
F = Framing bit L = dc balancing bit D = D-channel bit E = Echo D-channel bit
FA = Auxiliary framing bit or Q-channel bit N = Bit set to binary value N = FA A = Activation bit S = S-channel bit
M = Multiframe synchronization bit B1 = Bit within B channel 1 B2 = Bit within B channel 2
Signals from NT to TE INFO 0 INFO 2 No signal. INFO 0 Frame with all bits of B, D, and D echo (E) channels set to INFO 1 binary ZERO; bit A set to binary ZERO; N and L bits set according to the normal coding rules.
Signals from TE to NT No signal. A continuous signal with the following pattern: positive ZERO, negative ZERO, six ONEs.
INFO 4
Frames with operational data on B, D, and E channels; bit A set to binary ONE.
INFO 3
Synchronized frames with operational data on B and D channels.
5-2480 (C)
Figure 6. Details of NT and TE Frames
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
U-Interface Description
At the U-interface, the T7234 conforms to ANSI T1.601 and ETSI ETR 080 when used with the proper line interface circuitry. The T7234 Reference Circuit description in the Application Briefs section of this document describes a detailed example of a U-interface circuit design. The 2B1Q line code provides a four-level (quaternary) pulse amplitude modulation code with no redundancy. Data is grouped into pairs of bits for conversion to quaternary (quat) symbols. Figure 7 shows an example of this coding method. The U-interface transceiver section provides the 2B1Q line coder (D/A conversion), pulse shaper, line driver, first-order line balance network, clock regeneration, and sigma-delta A/D conversion. The line driver, when connected to the proper transformer and interface circuitry, generates pulses which meet the required 2B1Q templates. The A/D converter is implemented by using a double-loop, sigma-delta modulator. The U-transceiver block also takes input from the data flow matrix and formats this information for the U-interface (see Figure 1). During this formatting, synchronization bits for U framing are added and a scrambling
algorithm is applied. This data is then transferred to the 2B1Q encoder for transmission over the U-interface. Signals received from the U-interface are first passed through the sigma-delta A/D converter, and then sent to the digital signal processor for more extensive signal processing. The block provides decimation of the sigma-delta output, linear and nonlinear echo cancellation, automatic gain control, signal detection, phase shift interpolation, decision feedback equalization, timing recovery, descrambling, and line-code polarity detection. The decision feedback equalizer circuit provides the functionality necessary for proper operation on subscriber loops with bridged taps. A crystal oscillator provides the 15.36 MHz master clock for the device. The on-chip, phase-locked loop provides the ability to synchronize the chip to the line rate. The U-interface provides rapid cold start and warm start operation. From a cold start, the device is typically operational within four seconds. The interface supports activation/deactivation, and when properly deactivated, it stores the adaptive filter coefficients permitting a warm start on the next activation request. A warm start typically requires 200 ms for the device to become operational.
+3 +1 -1 -3 QUAT SYMBOL BIT CODING -1 01 +3 10 +1 11 -3 00 -3 00 +1 11 +3 10 -3 00 -1 01 -1 01 +1 11 -1 01 -3 00 +3 10 +3 10 -1 01 +1 11
5-2294 (C)
Figure 7. U-Interface Quat Example
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
The line receiver is more complex. Since the loop length to the subscriber(s) is variable, as is the number of TEs on the loop (1 to 8), the receiver must be sufficiently intelligent to adjust for widely varying input waveforms. The receiver uses a self-adjusting voltage threshold comparator to adapt to various loop lengths. It also features a digital timing recovery circuit employing either adaptive or fixed timing modes. The adaptive timing mode can be used on any loop configuration (point-to-point, extended passive bus, short passive bus) in which round trip delays are between 0 s and 42 s and differential delays between TEs are between 0 s and 3.1 s. This exceeds the requirement in the standards, which is 0--2 s (see, for example, ITU-T I.430 section A.2.1.3, p. 58). A differential delay of 0 s is meaningful in the case of a line transmitter and line receiver directly connected externally in a loopback configuration, so the receiver can extract the 2B+D information correctly from the transmitted stream. A short passive bus configuration permits TEs to be connected anywhere along the full length of the cable, with the restriction that the total round trip delay must be between 10 s and 14 s for all TEs. Thus, worst-case differential delay between TEs can be as much as 4 s. If the differential delay is more than 3.1 s, adaptive timing mode cannot be used. A fixed timing mode is available for this case. When using fixed timing, the input stream is sampled 4.2 s after the leading edge of each 192 kHz transmit bit interval. The fixed/adaptive timing mode is controlled via the FTE pin.
S/T-Interface Description
At the S/T-interface, the 4-wire line transceiver meets the ANSI T1.605 standard, ITU-T I.430 recommendation, and ETSI ETS 300 012 when used with the proper line interface circuitry. Refer to the March 1996, T7903 ISA Multiport Wide Area Connection (ISA-MWAC) Device Data Sheet (DS96-084ISDN). Appendix F of the ISA-MWAC data sheet is an application brief that contains detailed information concerning guidelines for S/T line interface circuit design. The S/T transceiver interprets the frames received from the line and generates frames to be transmitted onto the S/T link. It exchanges full-duplex 2B+D information with the data flow matrix. The transceiver consists of two sections: the transmitter and the receiver. The transmitter is a voltage-limited current source. The transmitted bits are timed by an internal 192 kHz clock derived from the U-interface. The transmitter employs a line coding technique referred to in the standards as "pseudo-ternary coding with 100% pulse width," which is often referred to as alternate space inversion (ASI) coding. ASI coding represents a logical 1 by the absence of a pulse and a logical 0 by alternating positive and negative pulses. ASI is a differential strategy, with positive and negative rails connecting to the transformer. Current flows through the transformer only when there is a voltage difference on the two rails. When a logical one or mark is being sent, meaning no current is desired, both rails go to a high-impedance condition. When a positive logical zero (space) is transmitted, the positive rail forces current to the negative rail through the transformer. The reverse occurs for a negative zero. Table 3 and Figure 8 illustrate the ASI coding method. Table 3. Line Transmission Code Positive Rail Z* 1 0 Negative Rail Z* 0 1 Current 0 +1 -1 Logic 1 +0 -0
1
0
1 0
0
1
1 0
5-2295 (C)
Figure 8. S/T-Interface ASI Example
* Z = high impedance.
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Loopbacks
The figure below shows the Layer-1 loopbacks that are defined in ITU-T I.430, Appendix I and ANSI Specification T1.605, Appendix G. A complete discussion of these loopbacks is presented in ITU-T I.430, Appendix I.
If a U-interface transparent B1 or B2 loopback is requested via an eoc message, the proper channel is looped upstream of the data flow matrix. All other device functions are unaffected. If a U-interface transparent 2B+D loopback is requested via an eoc message, the 2B+D data will be looped as close to the S/T-interface as possible. The device forces all 0s in the echo channel towards the TE.
TE1
NT2
NT1
A
4
S
B1
3
B2
T
2
C
U
LT
TE2
TA
R
A
4
S
TE1 = ISDN terminal TE2 = Non-ISDN terminal TA = Terminal adapter NT2 = Network termination 2 NT1 = Network termination 1 LT = Line termination
R = R reference point S = S reference point T = T reference point U = U reference point
Loopback 2 3 4 C B1 or B2 A
Channel(s) Looped 2B+D channels 2B+D channels B1, B2 B1, B2 2B+D, B1, B2 2B+D, B1, B2
5-2482.a (C)
Figure 9. Location of the Loopback Configurations (Reference ITU-T I.430 Appendix I)
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Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Note: The ETSI state names begin with the letters NT instead of H. Also, the ETSI state tables do not include a state NT11 because it is considered identical to state NT6. Table A3 of the ETSI standard contains the additional states NT6A, NT7A, and NT8A to describe state related to the eoc loopback 2 (2B+D loopback). The most likely ANSI state for each STLED state is shown in bold typeface, in Table 4.
STLED Description
The STLED pin is used to drive an LED and provides a visual indication of the current state of the T7234. The STLED control is typically configured to illuminate the LED when STLED is LOW. This convention will be assumed throughout this section. Table 4 describes the four states of STLED, the list of system conditions that produce the state, and the corresponding ANSI states, as defined in ANSI T1.6011992 (Tables C1 and C4) and ETSI ETR 080-1992 (Tables A3 and I2).
The flow chart in Figure 10 illustrates the priority of the logic signals which control the STLED pin. Note that quiet mode and ILOSS mode are ANSI maintenance modes, and aib is a U-interface overhead bit.
Table 4. STLED States STLED State High (LED off) List of System Conditions that Can Cause STLED State RESET (pin 43) = 0 AUTOCTL = 0 or AUTOEOC = 0 or STOA = 0 U and S/T not active RESET = 0 Quiet mode active, or ILOSS mode active U activation attempt in progress AIB = 0 eoc-initiated 2B+D loopback active U active, S/T not fully active U and S/T fully active Corresponding ANSI States NA
8 Hz Flashing
H0, H1, H10, H12 NA
H2, H3, H4 H7, H8 NT6A*, NT7A*, NT8A* H6, H6(a), H7, H11, H8(a), H8(b), H8(c) H8
1 Hz Flashing Low (LED on) *
These are ETSI DTR/TM-3002 states not yet defined in ANSI T1.601, although they are defined in revised ANSI tables which are currently on the living list (i.e., not yet an official part of the standards document). State H8(a) is most likely when U-interface bit uoa = 0.
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
STLED Description (continued)
START
RESET PIN LOW? NO
YES
STLED = OFF
RESET = 0, QUIET YES MODE = ACTIVE, OR ILOSS STLED = 8 Hz MODE = ACTIVE
NO STLED = OFF YES S/T- AND U-INTERFACE INACTIVE? NO U-INTERFACE NOT SYCHRONIZED? NO STLED = 8 Hz YES aib = 0 NO LOOP2 = ACTIVE? NO STLED = 1 Hz YES INFO2 = 0? NO INFO4 = 0? YES STLED = 1 Hz
5-3599e (F)
YES
STLED = 8 Hz
YES
STLED = 8 Hz
NO
STLED = ON
Figure 10. STLED Control Flow Diagram
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
autonomous control of the metallic loop termination (MLT) maintenance is desired. The MLT capability implemented with the Lucent LH1465AB and an optocoupler provides a dc signature, sealing current sink, and maintenance pulse-level translation for the testing facilities. Maintenance pulses from the U-interface MLT circuit are received by the OPTOIN pin and digitally filtered for 20 ms. The device decodes these pulses according to ANSI maintenance state machine requirements and responds to each request automatically. For example, the T7234 will place itself in the quiet mode if six pulses are received from the MLT circuitry. Manual mode can be used in applications where an external maintenance decoder is used to drive the RESET and ILOSS pins of the T7234. In this mode, the RESET pin places the device in quiet mode and the ILOSS pin controls SN1 tone transmission.
eoc State Machine Description
The following list shows the eight eoc states defined in ANSI T1.601 and ETSI ETR 080. The bit pattern below represents the state of U-interface overhead bits eoci1--eoci8, respectively (see Table 2). 01010000--Operate 2B+D loopback. 01010001--Operate B1 channel loopback. 01010010--Operate B2 channel loopback. 01010011--Request corrupt CRC. 01010100--Notify of corrupted CRC. 11111111--Return to normal (default). 00000000--Hold state. 10101010--Unable to comply. The T7234 automatically handles the eoc channel processing per the ANSI and ETSI standards.
ANSI Maintenance Control Description
The ANSI maintenance controller of the T7234 can operate in fully automatic or in fully manual mode. Automatic mode can be used in applications where
Board-Level Testing
For board-level testing during manufacturing, the HIGHZ pin 3-states all digital outputs.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Application Briefs
T7234 Reference Circuit
A reference circuit illustrating the T7234 in a standalone NT1 application is shown in Figures 11 and 12. This depicts a complete stand-alone NT1 design with the exception of power supply circuitry and power status monitoring circuitry. A bill of materials for the schematic is shown in Table 5. Note that specific applications may vary depending on individual requirements. U-Interface The U-Interface attaches to the board at RJ-45 connector J1 (see Figure 11). F1 and VR2 provide overcurrent and overvoltage protection, respectively. These two devices in combination with transformer T1 provide protection levels required by FCC Part 68 and UL* 1459. For an in-depth discussion of protection issues, the following application notes are helpful. 1. "Overvoltage Protection of Solid-State Subscriber Loop Circuits," Lucent Analog Line Card Products Data Book (CA97-006ALC) 800372-2447. 2. Protection of Telecommunications Customer Premises Equipment, Raychem Corporation, 415-361-6900. C16 is a 1.0 F dc blocking capacitor that is required per ANSI T1.601, Section 7.5.2.3. The 250 V rating of C16 is governed by the maximum breakdown voltage of VR2, since the capacitor must not break down before VR2. The resistance of R13 (21 ) and F1 (12 ) provides a total line-side resistance of 33 , which is required when using the Lucent 2754H2 transformer (see the note at the end of Table 5 for information on R13 values when using other transformers). On the device side of the U-interface transformer, VR1 provides secondary overvoltage protection of 6.8 V. Optional capacitors C13 and C14 provide commonmode noise suppression for applications that are required to operate in the presence of high commonmode noise. R6 and R7 provide the necessary external hybrid resistors. S/T-Interface The S/T-interface attaches to the board at RJ-45 connector J2 (see Figure 12). L1 is a high-frequency common-mode choke used to minimize EMI. R24 and R25 are 100 terminations required by ITU I.430 Section 8.4. Jumper-selectable resistors R26 and R27 provide 18
for a 50 termination option instead of the standard 100 termination. This is useful in configurations where none of the TEs have terminating resistors. Dual-transformer T2 has a standard footprint that can accept ISDN transformers from several vendors. On the device side of the S/T-interface transformer, D2-- D11 and VR3--4 provide overvoltage protection for the device pins. R20--23 provide current limiting for cases where one or more of the protection diodes conducts due to an overvoltage condition. Capacitor C17 provides suppression of common-mode noise that might otherwise be introduced onto the receiver input pins, effectively increasing the receiver's CMRR. Note that the S/T transformer must have a center tap on the device side in order to use this scheme. R16 and R17 in combination with R20 and R21, respectively, provide the 121 of resistance required by the T7234 on each transmitter output pin. R18 and R19 are the 10 k, 10% resistors required on the receiver input pins. MLT Circuit The metallic loop termination (MLT) circuit (U3 and related components in Figure 11) provides a dc termination for the loop per ANSI T1.601, Section 7.5. R14 and R15 are power resistors used to sink current during overvoltage fault conditions. The optoisolater (U2) provides signal isolation and voltage translation of the signaling pulses used for NT maintenance modes, per T1.601, Section 6.5. The T7234 interprets these pulses via an internal ANSI maintenance state machine, and responds accordingly. For applications outside North America, the MLT circuit is not required. Status LED D1 in Figure 11 is an LED that is controlled by the STLED pin of the T7234 and indicates the status of the device (activating, out-of-sync, etc.). Table 4 and Figure 10 of this data sheet details the possible states of the STLED pin and the meaning of each state. Fixed/Adaptive Timing Control As detailed in Table 1, pin 7 of the T7234 controls whether the S/T-interface will use fixed or adaptive timing recovery. When there is no connection to pin 7, an internal 100 k pull-up holds the pin high, which causes the chip to default to adaptive timing recovery. JMP1 is provided (see Figure 11) to change the timing recovery mode to fixed timing by pulling pin 7 down through a 5.1 k resistor.
* UL is a registered trademark of Underwriters Laboratories, Inc. Raychem is a registered trademark of Raychem Corporation.
Lucent Technologies Inc.
Data Sheet February 1998
MLT CIRCUIT +5 V R11 137 POR CIRCUIT STATUS LED +5 V R4 825 +5 VA 7 HCPL-0701 2.2 M C5 1.0 F 5 R9 3 2 R15 1.1 k 2W D1 R5 5.1 k U2 +5 V R12 137 R8 17.8 k R10 10 k 8 6 LH1465AB 8 TC PR+ 7 RS T U3 6 PD R 5 COM PR- 1 2 3 4 R14 1.1 k 2W
Lucent Technologies Inc.
C15 (PLACE THIS CAPACITOR AS 0.1 F CLOSE AS POSSIBLE TO THE LH1465)
Application Briefs (continued)
C7 0.01 F C2 0.01 F
FOR NORTH AMERICAN APPLICATIONS ONLY
T7234 Reference Circuit (continued)
+5 V 40 41 42 43 44 1 2 3 4 5 6
+5 V 1 JMP1 2 C10 0.01 F +5 VA GNDA GNDA VDDA ILOSS RESET HIGHZ GND D OPTOIN STLED R3 5.1 k C9 820 pF T1 R6 16.9 R7 16.9 SA6.0CA VR1 5 9 1:1.5 2754H2 C11 0.01 F +5 VA C14 3300 pF C16 1 10 6 C13 3300 pF 7 R13 21
NOTE: THE WIDTH OF THESE TRACKS SHOULD BE 50 mils J1 1 2 F1 TR600-150 3 4 5 VR2 1.0 F 6 7 8 RJ-45 U-INTERFACE CIRCUIT SMP100-140
CONNECT PS1E AND PS2E TO POWER STATUS MONITORING CIRCUIT IF PRESENT SYN8K/LBIND VDDD
R1 5.1 k
R2 5.1 k
+5 V
C1 0.01 F
7 8 9 10 11 12 13 14 15 16 17 FTE PS2E PS1E GNDD ACTMODE SYN8K_CTL VDDD NC AUTOACT GNDD NC
T7234
VDDA SDINP SDINN HP LON GNDA VDDA LOP HN VRN VRP
39 38 37 36 35 34 33 32 31 30 29
VRCM RPR RNR GNDA TPR TNR VDDA X2 C6 0.1 F C8 0.1 F C12 0.1 F
28 27 26 25 24 23 22 21 X1 20 VDDO 19 GNDO 18
+5 V X1 15.360 MHz RNR TPR TNR RPR
Figure 11. T7234 Stand-Alone Reference Circuit-A
C3 0.01F C4 0.01 F +5 VA
GROUND/POWER PLANES SHOULD NOT COME WITHIN 2.5 mm OF THE CIRCUITRY WITHIN THIS DASHED AREA
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
5-4048.h (C)
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Application Briefs (continued)
T7234 Reference Circuit (continued)
S/T-INTERFACE CIRCUIT T2 TPR R16 75 D4 D8 VR3 R20 46.4 15 14 D5 D9 2 3 R24 100 16 1 1 JMP2 2 R26 100 4 13 4 3 2 12 5 1 JMP3 11 C17 0.1 F RNR R19 10 k D7 D11 R23 46.4 10 6 7 R25 100 2 R27 100 PE65554 RJ-45 1 1 2 L1 5 6 7 8 3 4 5 6 7 8 J2
TNR
R17 75
R21 46.4 R22 46.4
RPR
R18 10 k D2 D6 D3 D10 VR4
9
8
PE65498 2.5:1
5-4047(C).a
Note: See Question/Answer section, #35.
Figure 12. T7234 Stand-Alone Reference Circuit-B
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Application Briefs (continued)
T7234 Reference Circuit (continued)
Table 5. T7234 Reference Schematic Parts List Reference Designator C[1--4, 7, 10, 11] C5 C[6, 8, 12, 17] C9 C[13, 14] C15 Description Ceramic Chip Capacitor, 0.01 F, 10%, 50 V, X7R Tantalum Chip Capacitor, 1.0 F, 10%, 16 V Ceramic Chip Capacitor, 0.1 F, 10%, 50 V, X7R Ceramic Chip Capacitor, 820 pF, 5%, 50 V, NPO Ceramic Chip Capacitor, 3300 pF, 10%, 50 V, X7R Polyester Capacitor, 0.1 F, 63 V, 10% Note: Insulation resistance of this part must be >2 G. Capacitor, 1.0 F, 250 V, 10% Alternate: Philips 2222 373 41105 Green Surface-mount LED SMT Switching Diode Overcurrent Protector (Polyswitch5) Alternate: Bel Fuse6 MJS 1.00A, (201) 432-0463 See note at the end of this table (p. 23). RJ-45 8-pin Modular Jack (standard height) Two-position Header with Shorting Jumper High-frequency Common-mode Choke Alternate: Pulse PE-65854 (surface mount) SMC Resistor, 5.1 k, 1/8 W, 5% SMC Resistor, 825 , 1/8 W, 1% SMC Resistor, 16.9 , 1/8 W, 1% SMC Resistor, 17.8 k, 1/8 W, 1% SMC Resistor, 2.2 M, 1/8 W, 5% SMC Resistor, 10 k, 1/8 W, 5% SMC Resistor, 137 , 1/8 W, 1% SMC Resistor, 21.0 , 1 W, 1% Source Kemet1 Kemet Kemet Kemet Kemet Philips 2 Part # C1206C103K5RAC T491A105K016AS C1206C104K5RAC C0805C821J5GAC C1206C332F5RAC 2222 370 12104
C16
Vitramon 3, via TMI (rep)
(215) 830-8500
VJ9253Y105KXPM
D1 D[2--11] F1
Hewlett Packard 4 Philips Raychem
(415) 361-6900
HSMG-C650 PMLL4151 TR600-150
J1, J2 JMP[1--3] L1
Molex 7 Multiple Pulse Engineering 8
(619) 674-8100
15-43-8588 PE65554
R[1--3, 5] R4 R[6, 7] R8 R9 R[10, 18, 19] R[11, 12] R13
1. 2. 3. 4. 5. 6. 7. 8. 9.
Dale 9 Dale Dale Dale Dale Dale Dale Dale
CRCW1206512J CRCW12068250F CRCW120616R9F CRCW12061783F CRCW1206225J CRCW1206103J CRCW12061370F WSC-1
Kemet is a registered trademark of Kemet Laboratories Company, Inc. Philips is a registered trademark of Philips Manufacturing Company. Vitramon is a registered trademark of Vitramon, Inc. Hewlett Packard is a registered trademark of Hewlett-Packard Company. Polyswitch is a registered trademark of Raychem Corporation. Bel and Bel Fuse are registered trademarks of Bel Fuse, Inc. Molex is a registered trademark of Molex, Inc. Pulse Engineering is a registered trademark of Pulse Engineering, Inc. Dale is a registered trademark of Dale Electronics, Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Application Briefs (continued)
T7234 Reference Circuit (continued)
Table 5. T7234 Reference Schematic Parts List (continued) Reference Designator R[14, 15] R[16, 17] R[20--23] R[24--27] T1 Description SMC Resistor, 1.1 k, 2 W, 5% SMC Resistor, 75 , 1/8 W, 1% SMC Resistor, 46.4 , 1/8 W, 1% SMC Resistor, 100 , 1/8 W, 1% ISDN U-interface Transformer Source Dale Dale Dale Dale Lucent WSC-2 CRCW120675R0F CRCW120646R4F CRCW12061000F 2754H2 Alternates (See note at the end of this table, p. 23.): Lucent 2754K2 (1500 Vrms breakdown) Lucent 2809A (for EN60950 compliance) Valor 10 PT4084 (619) 537-2500 Midcom 671-7759 (605) 886-4385 PE65498 Alternates: Pulse Engineering PE-68988 (single transformer, reinforced insulation) Valor PT5048 (619) 537-2500 (pin compatible) Advanced Power Components11, LTD. APC40498 (pin compatible) APC2050S (single transformer, reinforced insulation) US: Terry Manton, Inc. (rep), (201) 447-8821 Europe: 44-634-290588 Vacuumschmelze12 (VAC) (single transformer, reinforced insulation) T60403-L4097-X017-80 U.S.: (908) 494-3530 Europe: 49-6181-38-2026 T7234 HCPL-0701 LH1465AB Part #
T2
ISDN S-interface Dual Transformer
Pulse Engineering
(619) 674-8100
U1 U2 U3
Single-chip NT1 IC, 44-pin PLCC Optocoupler ISDN dc Termination IC
Lucent Hewlett Packard Lucent
1. Kemet is a registered trademark of Kemet Laboratories Company, Inc. 2. Philips is a registered trademark of Philips Manufacturing Company. 3. Vitramon is a registered trademark of Vitramon, Inc. 4. Hewlett Packard is a registered trademark of Hewlett-Packard Company. 5. Polyswitch is a registered trademark of Raychem Corporation. 6. Bel and Bel Fuse are registered trademarks of Bel Fuse, Inc. 7. Molex is a registered trademark of Molex, Inc. 8. Pulse Engineering is a registered trademark of Pulse Engineering, Inc. 9. Dale is a registered trademark of Dale Electronics, Inc. 10. Valor is a registered trademark of Valor Electronics, Inc. 11. Advanced Power Components is a registered trademark of Advanced Power Technology, Inc. 12. Vacuumschmelze is a registered trademark of Vacuumschmelze GmbH.
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Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Application Briefs (continued)
T7234 Reference Circuit (continued)
Table 5. T7234 Reference Schematic Parts List (continued) Reference Designator VR1 Description Transient Voltage Suppressor Transient Voltage Suppressor Transient Voltage Suppressor, 6.8 V 15.36 Crystal Source SGSThomson13 SGSThomson Motorola Part # SM6T6V8CA Alternates: Motorola SA6.5CA, P6KE6.8CA, P6KE7.5CA SMP100-140 Alternate: Teccor14 P1602AB (972) 580-7777 1.5SMC6.8AT3 Alternate: Motorola 1N6269A SRX5144 Alternates: MTRON15 4044-001 (605) 665-9321 2B Elettronica S.D.L. TP0648 39-6-6622432
VR2
VR[3,4]
X1
Saronix
(415) 856-6900
1. Kemet is a registered trademark of Kemet Laboratories Company, Inc. 2. Philips is a registered trademark of Philips Manufacturing Company. 3. Vitramon is a registered trademark of Vitramon, Inc. 4. Hewlett Packard is a registered trademark of Hewlett-Packard Company. 5. Polyswitch is a registered trademark of Raychem Corporation. 6. Bel and Bel Fuse are registered trademarks of Bel Fuse, Inc. 7. Molex is a registered trademark of Molex, Inc. 8. Pulse Engineering is a registered trademark of Pulse Engineering, Inc. 9. Dale is a registered trademark of Dale Electronics, Inc. 10. Valor is a registered trademark of Valor Electronics, Inc. 11. Advanced Power Components is a registered trademark of Advanced Power Technology, Inc. 12. Vacuumschmelze is a registered trademark of Vacuumschmelze GmbH. 13. SGS-Thomson is a registered trademark of SGS-Thomson Microelectronics, Inc. 14. Teccor is a registered trademark of Teccor, Inc. 15.MTRON is a registered trademark of MTRON Industries, Inc., a wholly owned subsidiary of Lynch* Corporation. * Lynch is a registered trademark of Lynch Corporation. Note: The Lucent 2754K2 and the Valor PT4084 have different winding resistances than the Lucent 2754H2, and therefore require a change to the line-side resistor (R15). In addition, if the Bel Fuse is used in place of the Raychem TR600-150 PTC at location F1 (which will sacrifice the resettable protection that the PTC provides), the line-side resistors must be adjusted to compensate for reduced resistance due to the removal of the PTC (12 ). The following table lists the necessary resistor values for these cases. Note that R15 is specified at 1%. This is due to the fact that the values were chosen from standard 1% resistor tables. When a PTC is used, the overall tolerance will be greater than 1%. This is acceptable, as long as the total line-side resistance is kept as close as possible to the ideal value. See Questions and Answers section, #6 for more details.
Table 6. Line-Side Resistor Requirements Transformer Lucent 2754H2 Lucent 2754K2 Lucent 2809A Valor PT4084 When Raychem TR600-150 Is Used R13 21 15.4 9.53 0 When Bel Fuse Is Used R13 33.2 27.4 21.5 10.7
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Data Sheet February 1998
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. External leads can be soldered safely at temperatures up to 300 C. Parameter dc Supply Voltage Range Power Dissipation (package limit) Storage Temperature Voltage (any pin) with Respect to GND Symbol VDD PD Tstg -- Min -0.5 -- -55 -0.5 Max 6.5 800 150 6.5 Unit V mW C V
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to defined the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and, therefore, can be used for comparison. The HBM ESD threshold presented here was obtained by using these circuit parameters: ESD Threshold Voltage Device Voltage T7234-ML2 >1000
Recommended Operating Conditions
Parameter Ambient Temperature Any VDD GND to GND Symbol TA VDD VGG Test Conditions VDD = 5 V 5% -- -- Min -40 4.75 -10 Typ -- 5.0 -- Max 85 5.25 10 Unit C V mV
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Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Electrical Characteristics
All characteristics are for a 15.36 MHz crystal, 135 line load, random 2B+D data, TA = -40 C to +85 C, VDD = 5 V 5%, GND = 0 V, and output capacitance = 50 pF.
Power Consumption
Table 7. Power Consumption Parameter Power Consumption Power Consumption Test Conditions Operating, random data Powerdown mode Min -- -- Typ 270 35 Max 350 50 Unit mW mW
Pin Electrical Characteristics
Table 8. Digital dc Characteristics (Over Operating Ranges) Parameter Input Leakage Current: Low High Low High Input Voltage: Low High Low-to-high Threshold High-to-low Threshold Low High Output Leakage Current: Low High Low High Low High Output Voltage: Low, TTL Symbol IILPU IIHPU IILPD IIHPD VIL VIH VILS VIHS VILC VIHC IOZL IOZH IOZLPU IOZHPU IOZLPD IOZHPD VOL Test Conditions VIL = 0 (pins 2, 6, 7, 11, 44) VIH = VDD (pins 2, 6, 7, 11, 44) VIL = 0 (pins 8, 9, 12, 15, 43) VIH = VDD (pins 8, 9, 12, 15, 43) All pins except 2, 6, 43 All pins except 2, 6, 43 Pin 43 Pin 43 Pins 2, 6 Pins 2, 6 VOL = 0, Pin 44 = 0 (pins 3, 14) VOH = VDD, Pin 44 = 0 (pins 3, 14) VOL = 0, Pin 44 = 0 (pin 11) VOH = VDD, Pin 44 = 0 (pin 11) VOL = 0, Pin 44 = 0 (pins 4, 8, 9, 17) VOH = VDD, Pin 44 = 0 (pins 4, 8, 9, 17) IOL = 4.5 mA (pin 3) IOL = 19.5 mA (pins 4, 9) IOL = 8.2 mA (pins 8, 17) IOL = 6.5 mA (pin 14) IOL = 3.3 mA (pin 11) IOH = 32.2 mA (pins 4, 9) IOH = 13.5 mA (pins 8, 17) IOH = 10.4 mA (pins 3, 14) IOH = 5.1 mA (pin 11) Min -52 -- -10 -10 -- 2.0 VDD - 0.5 -- -- 0.7 VDD -- -10 -52 -- -10 10 -- -- -- -- -- 2.4 2.4 2.4 2.4 Max -10 -10 -- -52 0.8 -- -- 0.5 0.2 VDD -- 10 -- -10 10 -- 52 0.4 0.4 0.4 0.4 0.4 -- -- -- -- Unit A A A A V V V V V V A A A A A A V V V V V V V V V
High, TTL
VOH
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Data Sheet February 1998
Electrical Characteristics (continued)
S/T-Interface Receiver Common-Mode Rejection
Table 9. S/T-Interface Receiver Common-Mode Rejection Parameter Common-mode Rejection (at device pins) Symbol CMR Specifications 400 Unit mV
Crystal Characteristics
Table 10. Fundamental Mode Crystal Characteristics These are the characteristics of a parallel resonant crystal for meeting the 100 ppm requirements of T1.601 for NT operation. The parasitic capacitance of the PC board to which the T7234 crystal is mounted must be kept within the range of 0.6 pF 0.4 pF. Parameter Center Frequency Tolerance Including Calibration, Temperature Stability, and Aging Drive Level Series Resistance Shunt Capacitance Motional Capacitance Table 11. Internal PLL Characteristics Parameter Total Pull Range Jitter Transfer Function Jitter Peaking Test Conditions -- -3 dB point (NT), 18 kft 26 AWG 1.5 Hz typical Min 250 -- -- Typ -- 5* 1.0* Max -- -- -- Unit ppm Hz dB Symbol FO TOL DL RS CO CM Test Conditions With 25.0 pF of loading -- Maximum Maximum -- -- Specifications 15.36 70 0.5 20 3.0 20% 12 20% Unit MHz ppm mW pF fF
* Set by digital PLL; therefore, variations track U-interface line rate.
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Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Timing Characteristics
Table 12. RESET Timing Parameter tRSLFL, tFLRSH tRSLRSH Description RESET Setup and Hold Time RESET Low Time: From Idle Mode or Normal Operation From Power-on Min 60 375 1.5 Max -- -- -- Unit ns s ms
SYN8K tRSLFL RESET tRSLRSH
5-3462 (C)
tFLRSH
Figure 13. RESET Timing Diagram
Switching Test Input/Output Waveform
2.4 V 2.0 V TEST POINTS 0.8 V 0.4 V 0.8 V 2.0 V
2.4 V
0.4 V 5-2118 (C)
Figure 14. Switching Test Waveform
Propagation Delay
The maximum propagation delay from the S/T-interface to the U-interface (upstream direction) is 750 s. The maximum propagation delay from the U-interface to the S/T-interface (downstream direction) is 550 s.
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Data Sheet February 1998
Outline Diagram
44-Pin PLCC
Dimensions are in millimeters.
17.526 0.127 16.586 0.076 PIN #1 IDENTIFIER ZONE
6
1
40
7
39
16.586 0.076 17.526 0.127
17
29
18
28
4.572 MAX SEATING PLANE 1.27 TYP 0.51 MIN TYP 0.330/0.533 0.10
5-2506r8
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Lucent Technologies Sales Representative.
Ordering Information
Device Code T7234A - -ML-D T7234A - -ML-DT Shipping Method Dry Pack--Sticks Dry Pack--Tape & Reel Package 44-Pin PLCC 44-Pin PLCC Temperature -40 C to +85 C -40 C to +85 C Reliability -- -- Comcode 108051814 108050816
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Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Q6: The line interface components' specifications require 16.9 resistors on the line side of the transformer when using the 2754H2. For our application, we would like to change this value. Can the U-interface line-side circuit be redesigned to change the value of the line-side resistors? A6: Yes. For example, the line-side resistances can be reflected back to the device side of the transformer so that, instead of having 16.9 on each side of the transformer, there are no resistors on the line side of the transformer and 24.4 resistors on the device side (16.9 + 16.9 /N2, where N is the turns ratio of the transformer). Note that the reflected resistances should be kept separate from the device-side 16.9 resistors, and located between VR1 and T1 in Figure 11. This is necessary because the on-chip hybrid network (pins HP, HN) is optimized for 16.9 of resistance between it and the LOP/LON pins. Q7: Table 5, T7234 Reference Schematic Parts List, states the 0.1 F capacitor that is used with the LH1465 (C15) must have an insulation resistance of >2 G. Why? A7: This capacitor is used to set the gate/source voltage for the main transistor in the device. The charging currents for this capacitor are on the order of microamps. Since the currents are so small, it is important to keep the capacitor leakage to a minimum. Q8: The dc blocking capacitor (C16 in Figure 11) specified is 1.0 F. Can it be increased to at least 2 F? A8: This value can be increased to 2 F without an effect on performance. However, for an NT1 to be compliant with T1.601-1992 Section 7.5.2.3, the dc blocking capacitor must be 1.0 F 10%. Q9: Why is the voltage rating on 1 F dc blocking capacitor (C16 in Figure 11) so high (250 V)? A9: In Appendix B of T1.601, the last section states that consideration should be given to the handling of three additional environmental conditions. The third condition listed is maximum accidental ringing voltages of up to -200.5 V peak whose cadence has a 33% duty cycle over a 6 s period.
Questions and Answers
Introduction
This section is intended to answer questions that may arise when using the T7234 Single-Chip NT1 Transceiver. The questions and answers are divided into three categories: U-interface, S/T-interface, and miscellaneous.
U-Interface
Q1: Is the line interface for the T7234 the same as for the T7264? A1: Yes. The U-interface section on these chips is identical, so their line interfaces are also identical. Q2: Why is a higher transformer magnetizing inductance used (as compared to other vendors)? A2: It has been determined that a higher inductance provides better linearity. Furthermore, it has been found that a higher inductance at the far end provides better receiver performance at the near end and better probability of start-up at long loop lengths. Q3: Can the T7234 be used with a transformer that has a magnetizing inductance of 20 mH? A3: The echo canceler and tail canceler are optimized for a transformer inductance of approximately 80 mH and will not work with lower inductance transformers. Q4: Are the Lucent Technologies U-interface transformers available as surface-mount components? A4: Not at this time. Q5: Are there any future plans to make a smaller height 2-wire transformer? A5: Due to the rigid design specifications for the transformer, vendors have found it difficult to make the transformer any smaller. We are continuing to work with transformer vendors to see if we can come up with a smaller solution.
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Data Sheet February 1998
Questions and Answers (continued)
U-Interface (continued)
A9: (continued) This statement could be interpreted to mean that a protector such as VR2 in Figure 11 should not trip if subjected to a voltage of that amplitude. This interpretation sets a lower limit on VR2's breakover rating. Since capacitor C16 will be exposed to the same voltage as VR2, its voltage rating must be greater than the maximum breakover rating of VR2. This sets an upper limit on the protector breakover voltage. The result is a need for a capacitor typically rated at about 250 V. However, an argument can be made that it doesn't matter whether VR2 trips under this condition, since it is a fault condition anyway, and a tripped protector won't do any damage to a central office ringer. The only other similar requirement, then, is found in Footnote 8, referenced in Section 7.5.3 of ANSI T1.601. The footnote implies that the maximum voltage that an NT will see during metallic testing is 90 V. The breakover voltage VR2 must be large enough not to trip during the application of the test voltage mentioned in the footnote. This means that a protector with a minimum breakover voltage of 90 V can be used that would permit a capacitor of lower voltage rating (e.g., 150 V) to be used. This is the approach we currently favor, although Figure 11 illustrates the more conservative approach. Q10: What is the purpose of the 3300 pF capacitors (C13 and C14) in Figure 11 in the data sheet? A10: The capacitors are for common-mode noise rejection. The ANSI T1.601 specification contains no requirements on longitudinal noise immunity. Therefore, these capacitors are not required in order to meet the specification. However, there are guidelines in IEC 801-6 which suggest a noise immunity of up to 10 Vrms between 150 kHz and 250 MHz. At these levels, the 10 kHz tone detector in the T7234 may be desensitized such that tone detection is not guaranteed on long loops. The 3300 pF was selected to provide attenuation of this common-mode noise so
that tone detector sensitivity is not adversely affected. Since the 3300 pF capacitor was selected based only on guidelines, it is not mandatory, but it is recommended in applications which may be susceptible to high levels of common-mode noise. The final decision depends on the specific application. As for the size of the capacitors, lab tests indicate the following: 1. The performance of the system suffers no degradation until the values are increased to about 0.1 F. 2. The return loss at 25 kHz increases with increasing capacitor value. 3. The capacitor value has no effect on longitudinal balance. 4. A large unbalance in the capacitor values did not affect return loss, longitudinal balance, or performance. Q11: Are there any recommended common-mode filtering parts for the U-interface? I suspect that our product may have emissions problems, and I want to include a provision for common-mode filtering on the U-interface. A11: The only common-mode filtering parts we have any data on are two common-mode chokes from Pulse Engineering (619-674-8100) that are intended to help protect against external common-mode noise. The part numbers are PE-68654 (12.5 mH) and PE-68635 (4.7 mH), and in lab experiments, no noticeable degradation in transmission performance was observed. These chokes are typically effective in the frequency range 100 kHz--1 MHz. As far as emissions are concerned, we don't have a lot of data. We have seen some success with the use of RJ-45 connectors that have integral ferrite beads such as those from Corcom*, Inc., (708) 680-7400. These provide some flexibility in that they have the same footprint as some standard RJ-45 connectors.
* Corcom is a registered trademark of Corcom, Inc.
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Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Figure 15 is derived from the return loss template in ANSI T1.601. Return loss is a measure of the match between two impedances on either side of a junction point. The following equation is an expression of return loss in terms of the complex impedances of the two halves of the circuit Z1, Z2. RL (dB) = 20 log Z1 + Z2 -----------------Z1 - Z2
Questions and Answers (continued)
U-Interface (continued)
Q12: I am planning on using a Raychem PTC (p/n TR600-150) on the U-interface of the T7234 as shown in Figure 11. The device is rated at 6 -- 12 . I am concerned about the loose tolerance on the PTC resistance. Will I be able to pass the return loss requirements in ANSI T1.601 Section 7.1? A12: The NT1 impedance limits looking into tip/ring are derived from the T1.601 return loss requirements (Figure 9 in T1.601). At the narrowest point in the templates, the permissible range is between 111 to 165 . The tolerance on the PTC will reduce the impedance margin somewhat, but should still be acceptable.
When the impedances are not matched, the junction becomes a reflection point. For a perfectly matched load, the return loss is infinite, whereas for an open or short circuit, the return loss is zero. The return loss expresses the ratio of incident to reflected signal power and should consequently be fairly high.
10000
UPPER BOUND > 165 1000
IMPEDANCE ()
100
LOWER BOUND < 110.4 10
1 1.0 1.4 2.0 2.8 4.0 5.6 7.9 11.2 15.8 22.4 31.6 44.7 63.1 89.1 125.9 177.8 251.2
FREQUENCY (kHz)
5-4056 (C)
Figure 15. Transceiver Impedance Limits
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Data Sheet February 1998
Questions and Answers (continued)
U-Interface (continued)
A12: (continued) It is desirable to express the return loss in terms of impedance bounds, since an impedance measurement is relatively simple to make. From the above equation, upper and lower bounds on impedance magnitude can be derived as follows: ZO = return loss reference impedance = 135 ZU = upper impedance curve ZL = lower impedance curve Upper bound (ZU > ZO): RL (dB) = 20 log Lower bound (ZL < ZO): RL (dB) = 20 log ZO + ZL ------------------ZU - ZL ZO + ZU ------------------ZU - ZO
Q13: Why must secondary protection, such as a SGSThomson SM6T6V8CA protection diode, be used? A13: The purpose of the diode is to protect against metallic surges below the breakdown level of the primary protector. Such metallic surges can be coupled through the transformer and could cause device damage if the currents are high. The protector does not provide absolute protection for the device, but it works in conjunction with the built-in protection on the device leads. The breakdown voltage level for secondary protection devices must be chosen to be above the normal working voltage of the signal and typically below the breakdown voltage level of the next stage of protection. The SM6T6V8CA has a minimum breakdown voltage level of 6.4 V and a maximum breakdown voltage of 7.1 V. The chip pins that the SM6T6V8CA protects are pins 36 (HP), 31 (HN), 32 (LOP), and 35 (LON). The 16.9 resistors will help to protect pins 32 and 35, but pins 31 and 36 will be directly exposed to the voltage across the SM6T6V8CA. The on-chip protection on these pins consists of output diodes and a pair of polysilicon resistors. These pins have been thoroughly tested to ensure that a 7.1 V level will not damage them; therefore, no third level of protection is needed between the SM6T6V8CA and the HP and HN pins. The SM6T6V8CA has a maximum reverse surge voltage level of 10.5 V at 57 A. Sustained currents this large on the device side of the transformer are not a concern in this application. Thus, there should never be more than 7.1 V across the SM6T6V8CA, except for possibly an ESD or lightning hit. In these cases, the T7234 is able to withstand at least 1000 V (human-body model) on its pins.
Note that the higher the minimum return loss requirement, the tighter the impedance limits will be around ZO, and vice-versa. So, for the upper bound, solve for ZU:
---------- ------ 10 20 + 1 1 + 10 20 ZU = ZO ---------------------- = ZO ------------------------- - RL RL ---------------- 10 20 - 1 1 - 10 20 RL - RL
For the lower bound, solve for ZL:
---------- ------ 10 20 - 1 1 - 10 20 ZU = ZO ----------------------- = ZO -------------------------- - RL RL ---------------- 10 20 + 1 1 + 10 20 RL - RL
Plotting the above equations (using 135 for ZO and Figure 16 in T1.601 for the RL values) results in the graph shown in Figure 15, which shows the return loss expressed in terms of impedance upper and lower bounds.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
ensure that a 7.4 V level will not damage them; therefore, no third level of protection is needed between the SM6T6V8CA and the HP and HN pins. Q16: Can the range of the T7234 on the U-interface be specified in terms of loss? What is the range over straight 24 awg wire? A16: ANSI Standard T1.601, Section 5.1, states that transceivers meeting the U-interface standard are intended to operate over cables up to the limits of 18 kft (5.5 km) 1300 resistance design. Resistance design rules specify that a loop (of singleor mixed-gauge cable; e.g., 22 awg, 24 awg, and 26 awg) should have a maximum dc resistance of 1300 , a maximum working length of 18 kft, and a maximum total bridged tap length of 6 kft. The standard states that, in terms of loss, this is equivalent to a maximum insertion loss of 42 dB @ 40 kHz. Lucent Technologies has found that, for assessing the condition of actual loops in the field in a 2B1Q system, specifying insertion loss as 33.4 dB @ 20 kHz more closely models ANSI circuit operation. This is equivalent to a straight 26 awg cable with 1300 dc resistance (15.6 kft). The above goals are for actual loops in the outside loop plant. These loops may be subjected to noise and jitter. In addition, as mentioned above, there may be bridge taps at various points on the loop. The T1.601 standard defines 15 loops, plus the null, or 0-length loop, which are intended to represent a generic cross section of the actual loop plant. A 2B1Q system must perform over all of these loops in the presence of impairments with an error rate of <1e-7. Loop #1 (18 kft, where 16.5 kft is 26 awg cable and 1.5 kft is 24 awg cable) is the longest, so it has the most loss (37.6 dB @ 20 kHz and 47.5 dB @ 40 kHz). Note that this is more loss than discussed in the preceding paragraph. The difference is based on test requirements vs. field deployment. The test requirements are somewhat more stringent than the field goal in order to provide some margin against severe impairments, complex bridged taps, etc.
Questions and Answers (continued)
U-Interface (continued)
Q14: Where can information be obtained on lightning and surge protection requirements for 2B1Q products? A14: Requirements vary among applications and between countries. ANSI T1.601, Appendix B, provides a list of applicable specifications to which you may refer. Also, there are many manufacturers of overvoltage protection devices who are familiar with the specifications and would be willing to assist in surge protection design. The ITU-T K series recommendations are also a good source of information on protection, especially recommendation K.11, "Principles of Protection Against Overvoltages and Overcurrents," which presents an overview of protection principles. Also refer to the application notes mentioned in the U-interface Description section of this data sheet. Q15: ITU-T specification K.21 describes a lightning surge test for NT1s (see Figure 1/K.21 and Table 1/K.21, Test #1) in which both Tip and Ring are connected to the source and a 1.5 kV voltage surge is applied between this point and the GND of the NT1. What are the protection considerations for this test? Are the HP and HN pins susceptible to damage? A15: The critical component in this test is the transformer since its breakdown voltage must be greater than 1.5 kV. Assuming this is the case, the only voltage that will make it through to the secondary side of the transformer will be primarily due to the interwinding capacitance of the transformer coils. This capacitance will look like an impedance to the common-mode surge and will therefore limit current on the device side of the transformer. The device-side voltage will be clamped by the SM6T6V8CA device. The maximum breakdown voltage of the SM6T6V8CA is 7.1 V. The 16.9 resistors will help protect the LOP and LON pins on the T7234 from this voltage. However, this voltage will be seen directly on pins 36 and 31 (HP and HN) on the T7234. The on-chip protection on these pins consists of output diodes and a pair of polysilicon resistors. These pins have been thoroughly tested to
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Questions and Answers (continued)
U-Interface (continued)
A16: (continued) If a transceiver can operate over Loop #1 errorfree, it should have adequate range to meet all the other loops specified in T1.601. Loop #1 has no bridged taps, so passing Loop #1 does not guarantee that a transceiver will successfully start up on every loop. Also, due to the complex nature of 2B1Q transceiver start-up algorithms, there may be shorter loops which could cause start-up problems if the transceiver algorithm is not robust. The T7234 has been tested on all of the ANSI loops per the T1.601 standard and passes them all successfully. Two loops commonly used in the lab to evaluate the performance of the T7234 silicon are as follows: Loop Bridge Taps Configuration (BT) Loss @ 20 kHz (dB) 38.7 37.1 Loss @ 40 kHz (dB) 49.5 46.5
the PHL is about 36 dB, which is 2 dB worse than on ANSI Loop #1. A signal-to-noise ratio (SNR) measurement can be performed on the received signal after all the signal processing is complete (i.e., at the input to the slicer in the decision feedback equalizer). This is a measure of the ratio of the recovered 2B1Q pulse height vs. the noise remaining on the signal. The SNR must be greater than 22 dB in order to operate with a bit error rate of <1e-7. With no impairments, the T7234 SNR is typically 32 dB on the18 kft/26 awg loop. When all ANSI-specified impairments are added, the SNR is about 22.7 dB, still leaving adequate margin to guarantee error-free operation over all ANSI loops. Finally, to estimate range over straight 24 awg cable, the 18 kft loop loss can be used as a limit (since the T7234 can operate successfully with that amount of loss) and the following calculations can be made:
Loss of 18 kft/26 awg loop @ 20 kHz Loss per kft of 24 awg cable @ 20 kHz 38.7 dB 1.6 dB
18 kft/26 awg 15 kft/26 awg
None Two at near end, each 3 kft/22 awg
38.7 dB --------------------------- = 24 kft 1.6 dB/kft Thus, the operating range over 24 awg cable is expected to be about 24 kft. Q17: What does the energy spectrum of a 2B1Q signal look like? A17: Figure A1 (curve P1) in the ANSI T1.601 standard illustrates what this spectrum looks like. Q18: Please clarify the meaning of ANSI Standard T1.601, Section 7.4.2, Jitter Requirement #3. A18: The intent of this requirement is to ensure that after a deactivation and subsequent activation attempt (warm start), the phase of the receive and transmit signals at the NT will be within the specified limits relative to what they were prior to deactivation. This is needed so that the LT, upon a warm-start attempt, can make an accurate assumption about the phase of the incoming NT signal with respect to its transmit signal. Note that the T7234 meets this requirement by design because the NT phase offset from transmit to receive is always fixed.
The T7234 is able to start up and operate errorfree on both of these loops. Neither of these loops is specified in the ANSI standard, but both are useful for evaluation purposes. The first loop is used because it is simple to construct and easy to emulate using a lumped parameter cable model, and it is very similar to ANSI Loop #1, but the loss is slightly worse. Thus, if a transceiver can start up on this loop and operate error-free, its range will be adequate to meet the longest ANSI loop. The second loop is used because, due to its difficult bridge tap structure and its length, it stresses the transceiver start-up algorithms more than any of the ANSI-defined loops. Therefore, if a transceiver can start up on this loop, it should be able to meet any of the ANSIdefined loops which have bridge taps. Also, on a straight 26 awg loop, the T7234 can successfully start up at lengths up to 21 kft. This fact, combined with reliable start-up on the 15 kft 2BT loop above, illustrates that the T7234 provides ample start-up sensitivity, loop range, and robustness on all ANSI loops. Another parameter of interest is pulse height loss (PHL). PHL can be defined as the loss in dB of the peak of a 2B1Q pulse relative to a 0-length loop. For an 18 kft 26 awg loop, 34
Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
senses the applied signal and triggers. This causes the transmitter to enter its low-impedance state, where it will remain until the T7234 start-up state machine times out (typically within 1.5 seconds, depending on the signal from the far end). Q21: What are the average cold start and warm start times? A21: Lab measurements have shown the average cold start time to be about 3.3 s--4.2 s over all loop lengths, and the average warm start time to be around 125 ms--190 ms over all loop lengths. Q22: What is the U-interface's response time to an incoming wakeup tone from the LT? A22: Response time is about 1 ms. Q23: What is the minimum time for a U-interface reframe after a momentary (<480 ms) loss of synchronization? A23: Five superframes (60 ms). Q24: Where is the U-interface loopback 2 (i.e., eoc 2B+D loopback) performed in the T7234? A24: It is performed just inside the chip at the S/T-interface. The S/T receiver is disconnected internally from the chip pins, and the S/T transmit signal is looped back to the receiver inputs so the S/T section synchronizes to its own signal. This ensures that as much of the data path as possible is being tested during the 2B+D loopback. Q25: Are the embedded operations channel (EOC) initiated B1 and B2 channel loopbacks transparent? A25: Yes, the B1 and B2 channel loopbacks are transparent, as is the 2B+D loopback. Q26: How can proprietary messages be passed across the U-interface? A26: The embedded operations channel (EOC) provides one way of doing this. ANSI standard T1.601 defines 64 8-bit messages which can be used for nonstandard applications. They range in value from binary 00010000 to 01000000. There is also a provision for sending bulk data over the EOC. Setting the data/message indicator bit to 0 indicates the current 8-bit EOC word contains data that is to be passed transparently without being acted on. Note that there is no response time requirement placed on the NT in this case (i.e., the NT does not have to echo the message back to the LT). Also note that this is currently only an ANSI provision and is not an ANSI requirement. The T7234 does support this provision. 35
Questions and Answers (continued)
U-Interface (continued)
Q19: I need a way to generate a scrambled 2B1Q data stream from the T7234 for test purposes (e.g., ANSI T1.601 Section 5.3.2.2, Total Power and Section 7.2, Longitudinal Output Voltage). How can I do this? A19: A scrambled 2B1Q data stream (the "SN1" signal described in ANSI T1.601 Table 5) can be generated by pulling ILOSS (pin 6) low on the T7234. Q20: We are trying to do a return loss measurement on the U-interface of the T7234 per ANSI T1.601 Section 7.1. We are using a circuit similar to the one you recommend in the data sheet. We have observed the following. When the chip is in FULL RESET mode (powered on but no activity on the U- or S/T-interfaces), the return loss is very low, i.e., the termination impedance appears to be very large relative to 135 and falls outside the boundaries of Figure 19 of ANSI T1.601. However, if we inject a 10 kHz tone before making a measurement, the return loss falls within the template. Why is it necessary to inject the 10 kHz tone in order to get this test to pass? Shouldn't a 135 impedance be presented to the network regardless of the state of the T7234 once it is powered on? A20: The return loss is only relevant when the transmitter section is powered on. When the transmitter is powered, it presents a low-impedance output to the U-interface. The transmitter must be held in this low-impedance state when the return loss and longitudinal balance tests are performed. This can be accomplished by pulling RESET low (pin 43). With the RESET pin held low, the transmitter is held in a low-impedance state where each of its differential outputs drives DV. In this state, it is prevented from transmitting any 2BIQ data and won't respond to any incoming wakeup tones. This is different than the ANSIdefined FULL RESET state that the chip enters after power-on or deactivation. In FULL RESET, the transmitter is powered down and in a highimpedance state, with only the tone detector powered on and looking for a far-end wakeup tone. The transmitter powers down when in FULL RESET state to save power and maximize the tone detector sensitivity. The reason that the chip behaves as it does in your tests is that your test begins with the transmitter in its FULL RESET state, causing the return loss to be very low. If a 10 kHz signal is applied, the tone detector Lucent Technologies Inc.
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Questions and Answers (continued)
U-Interface (continued)
Q27: What is the value of the ANSI T1.601 cso and nib bits in the 2B1Q frame? A27: cso and nib are fixed at 0 and 1, respectively, by the device. This is because the device always has warm start capability (CSO = 0), and NT1s are required to have nib = 1 per T1.601-1992. Q28: It looks like the U-interface sai and act bits that the T7234 transmits towards the LT always track one another. If this is the case, I don't understand why they are both needed. Can you explain the purpose of the sai bit and how it relates to the act bit? A28: The sai bit is equal to 1 when there is activity (INFO 1 or INFO 3) on the S/T-interface. The act bit is 1 whenever layer 1 transparency is established. Most of the time these bits are the same, but there are two situations where they will be different. 1. The sai bit can be used in conjunction with the uoa bit from the LT to support DSL-only activation as described in the ANSI and ETSI standards. The LT can request a U-only activation by setting uoa = 0, which will cause the S/Tinterface to remain in a deactivated state. If the TE requests an activation under these conditions by transmitting INFO 1 to the T7234, the sai bit will change from 0 to 1, indicating to the LT that there is activity on the S/T-interface so that the LT can respond accordingly. Typically, this means that LT will set uoa = 1 to exit the DSL-only condition so that layer-1 transparency can be established from TE to LT. Thus, in the case of a DSL-only activation, the T7234's sai bit is 1 and its act bit is 0 from the time a TE requests an activation until the following events occur: A. B. C. D. LT sets uoa = 1 towards the NT. The T7234 detects uoa = 1 and transmits INFO 2 on the S/T-interface. The TE synchronizes and transmits INFO 3 on the S/T-interface. Upon reception of the INFO 3 signal, the T7234 sets act = 1.
2. If a link is fully active, then the LT detects a transition of the NT act bit from 1 to 0, it is an indication of loss of layer-1 transparency. This can be caused by either (a) S/T loss of sync or (b) NT1 received INFO 0. Case (a) will result in an act = 0/sai = 1 combination, i.e., S/T sync is lost but there is still activity on the S/T-interface, meaning the TE is having trouble staying synchronized. Case (b) will result in an act = 0/ sai = 0 combination, i.e., no activity on the S/Tinterface (INFO 0), meaning the TE has been disconnected (there is no way the TE can legally send INFO 0 when the link is fully active because the TE is not allowed to initiate deactivation--only the LT is--so the only other possibility is that it has been disconnected or has failed). Note that this procedure allows the CO to determine whether the cause of loss of layer-1 transparency is a TE that is having synchronization problems or a TE that has been disconnected, based on the state of the sai bit when act = 0. The ANSI T1.601 and ETSI ETR 080 standards contain finite state matrices that describe DSL-only operation. The T7234 follows the behavior described in the matrices. Refer to those tables for detailed information on each of the states.
S/T-Interface
Q29: What is the S/T transformer's inductance? A29: For Lucent transformers 2768A or 2776, a minimum inductance of 22 mH is guaranteed. Q30: Can the S/T-interface leads be short-circuited together without harming the device? A30: Yes, this will not cause any harm to the device. Q31: What is the common-mode rejection of the S/T receiver? A31: The common-mode rejection of the S/T receiver is 400 mV. Refer to the Electrical Characteristics described in the data sheet.
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Q34: I would like to integrate a T7234-based NT1 onto both a T7250C-based 4-wire TE product and a T7903-based 4-wire TE product in order to provide a U-interface on these products. I realize this can be done by simply incorporating my external NT1 design directly onto the TE board, but is there a simpler approach in which I can avoid having two sets of S/T transformers and associated line interface circuitry? A34: Yes. First note Figures 17, 18, and 19, which show examples S/T line interface circuits for the T7234, T7903, and T7250C, respectively. If no external S/T-interface connection is required, the T7234 can be directly connected to the T7903 and T7250C as shown in Figures 20 and 21. If there is a requirement for connecting external TEs, the circuits shown in Figures 22 and 23 can be used. These two circuits show a hybrid scheme in which a direct connect between the T7234 and T7903/T7250C is implemented while providing for an external S/T-interface (thus requiring only one set of S/T transformers rather than the two sets that would be required if the T7234 and T7903/T7250C were transformer-coupled to one another instead directly connected). The direct connect circuits were derived as shown in Figures 20 and 21 and the following text sections: Note: In all of these analyses, the final value of resistance chosen may be slightly different than the ideal value computed because standard resistance values were used.
Questions and Answers (continued)
S/T-Interface (continued)
Q32: I notice that the application note entitled Design an S/T Line Interface Circuitry Using the T7250C/ T7259 recommends relays on both the transmitter and receiver outputs that disconnect the device when power is removed from the chip. Is this necessary for an NT using the T7234? A32: The relay on the TE transmitter output is necessary to pass the peak current test (ITU-T I.430 Section 8.5.1.2 and ANSI T1.605-1991, section 9.5.1.2) when the TE is powered down. For the NT, there is no equivalent test, so the relay is not necessary. The relay on the TE receiver input is also necessary to pass the peak current test (ITU-T I.430 Sections 8.5.1.2 and 8.6.1.1, and ANSI T1.605-1991 Sections 9.5.1.2 and 9.6.1.1). For the NT, however, there is enough margin in the line interface capacitance circuitry such that the peak current requirement (ITU-T I.430 Section 8.6.1.2 and ANSI T1.605-1991 Section 9.6.1.2) can be met without using relays. This assumes, of course, that sound layout practices have been applied to keep parasitic capacitance of the line interface circuitry to a minimum (of primary importance is making sure there is no ground plane under the S/T line interface). The reason the TE needs a relay on its receiver is that the TE tests assume a 350 pF cord connected to the line, and this extra capacitance can cause the peak current requirement to be exceeded. So even though the NT peak current requirement is slightly more stringent (0.5 mA as opposed to 0.6 mA), the TE peak current test is the most difficult to meet due to the 350 pF cord capacitance. Q33: The T7234 reference design in Figure 12 shows 100 termination resistors in parallel with a second pair of optional 100 resistors that can be inserted or removed by installing/removing jumpers from JMP1 and JMP2. What is the purpose of this second pair of resistors? A33: Typically, a TE or group of TEs connected to an NT1 will have a 100 termination located at the interface point of the TE farthest from the NT1 (refer to ITU-T I.430 Figure 2 and Section 4 or T1.605 Figure 2 and Section 5). However, in some cases it may be desirable to operate an NT1 with a TE that does not provide the 100 termination impedance. In this case, the provisional 100 resistors shown in Figure 12 may be installed to provide the extra termination impedance required. Lucent Technologies Inc.
T7903/T7250C Transmit to T7234 Receive a) Transmitter Load: T7903: The line interface transformer has a turns ratio of 2.0, and the transmitter drives a total line-side load of 50 . Reflecting this impedance to the device side of the transformer results in 200 (50 x N2). This resistance, combined with the 40 total resistance of the device-side resistors, results in a total of 240 that the transmitter typically drives. So, to optimize the transmitter part of the circuit based on the load the transmitter expects to drive, the transmitter should see a total resistance of approximately 240 .
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Questions and Answers (continued)
S/T-Interface (continued)
A34: (continued) T7250C: The line interface transformer has a turns ratio of 2.5, and the transmitter drives a line-side load of 50 . Reflecting this impedance to the device side of the transformer results in 312.5 (50 x N2). This resistance, combined with the 113 total resistance of the device-side resistors, results in a total of 425.5 that the transmitter typically drives. So, to optimize the transmitter part of the circuit based on the load the transmitter expects to drive, the transmitter should see a total resistance of approximately 425 . b) Receiver Levels: The T7234 S/T line interface transformer has a turns ratio of 2.5. The receiver expects to see nominal pulse levels of 750 mV x 2.5 = 1.875 V. T7903: The transmitter circuit is a current source of 7.5 mA. To generate a voltage of 1.875 V with 7.5 mA requires a resistance of 1.875/0.0075 = 250 . T7250C: The transmitter circuit is a current source of 6 mA. To generate a voltage of 1.875 V with 6 mA requires a resistance of 1.875/0.006 = 312.5 . c) Resistor Selection:
transmitter drove 6 mA through 312.5 . So, the total transmit path resistance should be divided into three resistors. The first is the resistor across which the receiver is connected and should be approximately 312.5 so that the receiver sees the correct levels. A standard 309 value is adequate for this case. The remainder of the 425 should be divided equally between two other series resistors in the transmit path, and (425 - 309 )/2 is 58.0 , so a standard 57.6 value is chosen for the two other series resistors as illustrated in Figure 21. d) Receiver Bias: Normally, the transmitter of theT7903/ T7250C is biased at 5 V through 100 k pullup, and the receiver of the T7234 is biased at 2.16 V through a resistor network that can be simplified as shown in Figure 16 (A). When the direct-connect scheme is implemented, the resulting network between the T7903/ T7250C transmitter and the T7234 receiver is as shown in Figure 16 (B).
5V 5V 5V
30 k 100 k 2.16 V CHIP PIN 23 k
100 k 10 k CHIP PIN 100 k
30 k 2.33 V CHIP PIN 23 k
(A)
(B)
5-4726
In this section, the term receiver implies not only the receive section on the chip, but also the external 10 k resistors connected to the receiver. These resistors remain unchanged from the standard line interface circuit in order to maintain the same total receiver impedance. T7903: Ideally, the transmitter should be driving into 240 , and the T7234 receiver wants to see the levels that would result if the transmitter drove 7.5 mA through 250 . Since these resistance values are so close, 249 is chosen as the resistor across which the receiver is connected, and no other series resistance is needed in the transmit path, as Figure 20 illustrates. T7250C: Ideally, the transmitter should be driving into 425 , and the T7234 receiver wants to see the levels that would result if the 38
Figure 16. Receiver Bias Note that the receiver bias in Figure 16 (B) is increased to 2.33 V (from 2.16 V in Figure 16 (A)). This is an increase of about 8% (0.67 dB). This will decrease the overall receiver sensitivity slightly. Normally, the receiver must have a sensitivity to signals down to -7.5 dB of nominal. Therefore, in the case of a direct connect, the sensitivity is not an issue since the receiver will always see a large input signal.
Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
connected and should be approximately 250 so that the receiver sees the correct levels. A standard 249 value is adequate for this case. The remainder of the 554.5 should be divided equally between two other series resistors in the transmit path, and (554.5 - 249 )/2 is 152.7 , so 150 is chosen for the two other series resistors as illustrated in Figure 20. T7250C: Ideally, the T7234 transmitter should be driving into 554.5 , and the T7250C receiver wants to see the levels which would result if the transmitter drove 6 mA through 312.5 . So, the total transmit path resistance should be divided into three resistors. The first is the resistor across which the receiver is connected and should be approximately 312.5 so that the receiver sees the correct levels. A standard 309 value is adequate for this case. The remainder of the 554.5 should be divided equally between two other series resistors in the transmit path, and (554.5 - 309 )/2 is 122.6 , so 121 is chosen for the two other series resistors as illustrated in Figure 21. d) Receiver Bias: The receiver bias is not an issue for the same reasons discussed in the T7903/T7250C Transmit to T7234 Receive section. T7903/T7250C to T7234 Direct Connect with External S/T-Interface Provided First, we need to address the issue of the transformer turns ratio. T7903: The T7903 uses a 2.0:1 transformer, and the T7234 uses a 2.5:1 transformer. It is desirable to be able to use a dual transformer, so we want the transmit- and receive-side transformers to have the same turns ratio. Also, it may be desirable to use a product with this arrangement as just a TE (with an external NT1, i.e., no U-interface connected to the integrated NT1). Therefore, we will select a 2.0:1 turns ratio transformer to ensure T7903 pulses of sufficient amplitude on the line side of the transformer and ensure that an external transmitter won't overdrive the T7903 receiver inputs. T7250C: The T7250C and T7234 both use a 2.5:1 transformer, which simplifies the analysis for this case.
Questions and Answers (continued)
S/T-Interface (continued)
A34: (continued) T7234 Transmit to T7903/T7250C Receive a) Transmitter Load: The T7234 S/T line interface transformer has a turns ratio of 2.5, and the transmitter drives a line-side load of 50 . Reflecting this impedance to the device side of the transformer results in 312.5 (50 x N2). This resistance, combined with the 242 total resistance of the device-side resistors, results in a total of 554.5 that the transmitter typically drives. So, to optimize the transmitter part of the circuit based on the load the transmitter expects to drive, the transmitter should see a total resistance of approximately 554.5 . b) Receiver Levels: T7903: The S/T line interface transformer has a turns ratio of 2.0. The receiver expects to see nominal pulse levels of 750 mV x 2.0 = 1.5 V. The T7234 transmitter circuit is a current source of 6.0 mA. To generate a voltage of 1.5 V with 6.0 mA requires a resistance of 1.5/0.006 = 250 . T7250C: The S/T line interface transformer has a turns ratio of 2.5. The receiver expects to see nominal pulse levels of 750 mV x 2.5 = 1.875 V. The T7234 transmitter circuit is a current source of 6.0 mA. To generate a voltage of 1.875 V with 6.0 mA requires a resistance of 1.875/0.006 = 312.5 . c) Resistor Selection: In this section, the term receiver implies not only the receive section on the chip, but also the external 10 k resistors connected to the receiver. These resistors remain unchanged from the standard line interface circuit in order to maintain the same total receiver impedance. T7903: Ideally, the T7234 transmitter should be driving into 554.5 , and the T7903 receiver wants to see the levels that would result if the transmitter drove 6 mA through 250 . So, the total transmit path resistance should be divided into three resistors. The first is the resistor across which the receiver is
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Questions and Answers (continued)
S/T-Interface (continued)
A34: (continued) T7903/T7250C Transmit to T7234 Receive a) Transmitter Load: If we use the same S/T-transmitter line interface circuit as in the normal (stand-alone TE) case, the transmitter will see the load that it expects to drive and is thus optimized in terms of the load. The 100 terminations must be user selected per the following table: Configuration JMP1 JMP2
in a short passive bus (SPB) mode when using the onboard NT1, because there is a local TE (the T7903), so any external TE that is also used will result in a passive bus configuration. ITU-T I.430 states that the maximum attenuation in SPB configuration is 3.5 dB. Combining this with the inherent 1.9 dB attenuation results in a total possible signal attenuation of 5.4 dB. The receiver must have a sensitivity of at least 7.5 dB per ITU-T I.430 Section 8.6.2.3, so 5.4 dB attenuation will present no problem in this case. T7250C: The T7250C transmitter (or an external TE on a 0-length loop) will drive 750 mV pulses on the S/T line, and that voltage reflected back to the device side of the transformer is 750 mV x 2.5 = 1.875 V. If theT7234 receiver is connected to the device side of the transformer as shown in Figure 23, it will see the 1.875 V pulse level it expects when a 750 mV pulse is present on the line. c) Receiver Bias: In the T7903 to T7234 Direct-Connect section we showed that the receiver is biased by about 0.67 dB from nominal due to the direct connect of the T7903 to the T7234. Assuming the receiver sensitivity decreases by this much and combining this with the maximum 5.4 dB attenuation found in the previous section results in a total of 6.07 dB of required sensitivity, which is still within the 7.5 dB requirement on the receiver. T7234 Transmit to T7903/T7250C Receive a) Transmitter Load: The T7234 S/T line interface transformer normally has a turns ratio of 2.5, and the transmitter drives a line-side load of 50 . Reflecting this impedance to the device side of the transformer results in 312.5 (50 x N2). This resistance, combined with the 242 total resistance of the device-side resistors, results in a total of 554.5 that the transmitter typically drives. So, to optimize the transmitter part of the circuit based on the load the transmitter expects to drive, the transmitter should see a total resistance of approximately 554.5 .
Integrated NT1 Used as NT1 (No External NT1 Connected) No External TE Connected Unterminated External TE Connected Terminated (100 ) External TE Connected b) Receiver Levels: The T7234 S/T line interface transformer has a turns ratio of 2.5. The T7234 receiver thus expects to see nominal pulse levels of 750 mV x 2.5 = 1.875 V at the device side of the transformer. T7903: The T7903 transmitter (or an external TE on a 0-length loop) will drive 750 mV pulses on the S/T line, and that voltage reflected back to the device side of the transformer is 750 mV x 2.0 = 1.5 V. If the T7234 receiver is connected to the device side of the transformer as shown in Figure 22, it will see 1.5 V instead of 1.875 V when a 750 mV pulse is present on the line. Thus, there is an inherent pulse attenuation in this scheme of 1.9 dB at the T7234 receiver. We need to be sure that the receiver will have adequate sensitivity to detect pulses from an external TE that is some distance away. Referring to ITU I.430, this circuit can only be used Installed Installed Installed Installed
Installed
Not Installed
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
T7250C: Referring to Figure 23, if we use the same T7234 S/T transmitter line interface circuit as in the normal (stand-alone NT) case, the T7234 transmitter will see the 554.5 load that it normally expects to drive and is thus optimized in terms of the load. The 100 terminations shown are user selected per the preceding table. b) Receiver Levels: The T7903 will see the correct pulse levels by design. In the preceding section, the T7234 transmit circuit was designed to produce 750 mV pulses on the line. The T7903 receiver is attached directly to the device side of the transformer, so it will see the 1.5 V pulse levels that it expects to see. T7903: The T7903 S/T line interface transformer has a turns ratio of 2.0. The T7903 receiver thus expects to see nominal pulse levels of 750 mV x 2.0 = 1.5 V at the device side of the transformer. The T7234 transmitter section was designed to produce 750 mV pulses on the S/T line (as would an external TE on a 0-length loop). That voltage reflected back to the device side of the T7901 transformer is 750 mV x 2.0 = 1.5 V, so the T7901 sees the pulse level it expects when a 750 mV pulse is present on the line. T7250C: The T7250C S/T line interface transformer has a turns ratio of 2.5. The T7250C receiver thus expects to see nominal pulse levels of 750 mV x 2.5 = 1.875 V at the device side of the transformer. The T7234 transmitter section was designed to produce 750 mV pulses on the S/T line (as would an external TE on a 0-length loop). That voltage reflected back to the device side of the T7250C transformer is 750 mV x 2.5 = 1.875 V, so the T7250C sees the pulse level it expects when a 750 mV pulse is present on the line. c) Receiver Bias: The receiver bias is sufficiently small that it is not an issue (see preceding sections).
Questions and Answers (continued)
S/T-Interface (continued)
A34: (continued) T7903: In this case, the T7234 transmitter is driving into a transformer with a turns ratio of 2.0. The pulse amplitude that the transmitter must generate on the device side of the transformer is 1.5 V (resulting in a 750 mV pulse on the line in accordance with the standards). The T7234 transmitter circuit is a current source of 6.0 mA. To generate a voltage of 1.5 V with 6.0 mA requires a resistance of 1.5/0.006 = 250 , which is 62.5 when reflected to the device side of the transformer. This impedance should consist of jumperselectable 100 and 167 resistors as illustrated in Figure 22. The table below lists the jumper settings for each possible configuration. The total impedance the T7234 must drive (from the first paragraph of this section) is 554.5 , and the impedance across the transformer leads is 250 (from the second paragraph). The remaining 554.5 - 250 = 304.5 is divided equally between the positive and negative transmitter outputs, requiring 152 in each leg. We can accomplish this with a 143 resistor on the device side of the diode bridge and a 10 resistor on the line side of the bridge. The resistance is split in this way to provide 10 of current limiting through the diode bridge when the bridge is conducting (similar to the T7903 transmitter circuit). Configuration JMP3 JMP4
Integrated NT1 Used as NT1 (No External NT1 Connected) No External TE Connected Unterminated External TE Connected Terminated (100 ) External TE Connected Installed Installed Installed Installed Installed Not Installed
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Questions and Answers (continued)
S/T-Interface (continued)
A34: (continued)
T7234 75 TPR D1 D2 6.8 V ZD1 D3 TNR 75 D4 46.4 46.4 6.8 V ZD2 D7 RNR 10 k D8 46.4
5-4721
46.4
T1 2.5:1 JMP1 100 100 T3 RJ-45 1 2 3 4 T2 2.5:1 JMP2 100 100 5 6 7 8
RPR 10 k D9 D10 D5 D6
C1 0.1 F
Figure 17. T7234 S/T Line Interface Scheme
T7903 10 NPx_PT D1 D2 6.8 V ZD1 D3 NPx_NT 10 D4 5 10 JMP2 6.8 V ZD2 D7 NPx_NR 10 k D8 10
5-4722
5
T1 2.0:1 JMP1 * 100 T3 RJ-45 1 2 T2 2.0:1 3 4 5 6 7 C1 0.1 F 100 8
NPx_PR 10 k D5 D6
* Refer to the T7903 data sheet, Figure F-10 for an example of a switch circuit that can be used here.
Figure 18. T7903 S/T Line Interface Scheme 42 Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Questions and Answers (continued)
S/T-Interface (continued)
A34: (continued)
T7250C 10 TPR D1 D2 6.8 V ZD1 D3 TNR 10 D4 46.5 T2 2.5:1 JMP2 100 * JMP1 100 T3 RJ-45 1 2 3 4 5 6 7 C1 0.1 F 8 46.5 T1 2.5:1
RPR 10 k D9 D10 D7 RNR 10 k 46.5 D8 D5 D6 46.5 6.8 V ZD2
5-4723
* Refer to the T7250 data sheet, Figure F-10 for an example of a switch circuit that can be used here.
Figure 19. T7250C S/T Line Interface Scheme Note: The circuit shown above has subtle differences from that shown in the T7250C data sheet. Either circuit is suitable, since they will both pass the required conformance tests.
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Questions and Answers (continued)
S/T-Interface (continued)
A34: (continued)
T7903 T7234
10 k NPx_PT 249 10 k NPx_NT RNR RPR
10 k NPx_PR 249 10 k NPx_PT
150 TPR
150 TNR
5-4724
Figure 20. T7903 to T7234 Direct-Connect Scheme
T7250C 57.6 309 57.6 TNR 10 k
T7234
10 k RPR
TPR
RNR
10 k RPR 309 10 k RNR
121 TPR
121 TNR
5-4725
Figure 21. T7250C to T7234 Direct-Connect Scheme
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Questions and Answers (continued)
S/T-Interface (continued)
A34: (continued)
5 D1 D2 6.8 V ZD1 D3 D4 5 T7903 NPx_PT NPx_NT T7234 10 k RPR T3 10 RNR 10 k RJ-45 1 2 3 T7234 10 k TPR TNR 143 143 10 k NPx_PR NPx_NR T7903 4 5 6 7 8 * T1 2.0:1 JMP1 100 JMP2 100
10
10 D5 D6 6.8 V ZD2 D7 D8 10 0.1 F
T2 2.0:1 JMP3 167 JMP4 100
5-4728
* Refer to the T7903 data sheet, Figure F-10 for an example of a switch circuit that can be used here.
Figure 22. T7903 to T7234 Direct-Connect Scheme with External S/T-Interface
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Questions and Answers (continued)
S/T-Interface (continued)
A34: (continued)
T1 2.5:1 JMP1 6.8 V * ZD1 D3 D4 46.5 T7250C TPR TNR T7234 10 k RPR T3 10 RNR 10 k RJ-45 1 2 3 T7234 10 k TPR TNR 75 75 10 k RPR RNR T7250C 4 5 6 7 8 100 100 JMP2
46.5 D1 D2
10
46.5 D5 D9 D10 D7 D8 46.5 D6 6.8 V ZD2 0.1 F
T2 2.5:1 JMP3 100 JMP4 100
5-4727
* Refer to the T7250 data sheet, Figure F-10 for an example of a switch circuit that can be used here.
Figure 23. T7250C to T7234 Direct-Connect Scheme with External S/T-Interface
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
quency to be adjusted to compensate for board parasitics. Can this be done with the T7234 crystal? Also, can we use a crystal from our own manufacturer? A38: For the T7234, these capacitors are located on the chip, so their values are fixed. The advantage to this is that no external components are required. The disadvantage is that board parasitics must be very small. The Crystal Characteristics section of the data sheet notes that the board parasitics must be within the range of 0.6 pF 0.4 pF. Q39: I plan to program the T7234 to output 15.36 MHz from its CKOUT pin. Is this clock a buffered version of the 15.36 MHz oscillator clock? I am concerned that if it is not buffered, the capacitive loading on this pin could affect the system clock frequency. A39: The 15.36 MHz output is a buffered version of the XTAL clock and therefore hanging capacitance on it will not affect the T7234's system clock frequency. Q40: How does the filtering at the OPTOIN input work? A40: The signals applied to OPTOIN are digitally filtered for 20 ms. Any transitions under 20 ms will be ignored. Q41: What is the isolation voltage of the 6N139 optoisolator used in the dc termination circuit of the T7234? A41: 2500 Vac, 1 minute. Q42: Can the T7234 operate with an external 15.36 MHz clock source instead of using a crystal? A42: Yes, by leaving X1 disconnected and driving X2 with an external CMOS-level oscillator. Q43: What is the effect of ramping down the powersupply voltage on the device? When will it provide a valid reset? This condition can occur when a line-powered NT1's line cord is repeatedly plugged in and removed and plugged in again before the power supply has had enough time to fully ramp-up. A43: The device's reset is more dependent on the RESET pin than the power supply to the device. As long as the proper input conditions on the RESET pin (see Table 12) are met, the device will have a valid reset. Note that this input is a Schmitt-trigger input.
Questions and Answers (continued)
S/T-Interface (continued)
Q35: In the Analog Interface section of the S/T-interface description in the data sheet, where does the value of 0 ms--3.1 ms maximum differential delay in adaptive timing mode come from? A35: The minimum value of 0 ms is necessary so that the NT's transmitter and receiver can be directly connected in a loopback and still synchronize. The maximum value of 3.1 ms comes about because the window size needed in the adaptive timing algorithm is 2.1 ms. The window size is the time during each bit period in which no transitions may occur. Since a period is 5.2 ms, the time during which there may be transitions is 5.2 ms - 2.1 ms, or 3.1 ms. This is the same as the maximum differential delay, since the earliest and latest bit transitions represent the nearest and farthest TEs relative to the NT receiver.
Miscellaneous
Q36: Is the 100 ppm free-run frequency recommendation met in the T7234? A36: In the free-run mode, the output frequency is primarily dependent on the crystal, not the silicon design. For low-cost crystals, initial tolerance, temperature, and aging effects may account for two-thirds of this budget, and just a couple of pF of variation in load capacitance will use up the rest; therefore, the 100 ppm goal can be met if the crystal parameters are well controlled. See the Crystal Characteristics section in this data sheet. Q37: What happens if Co and Cm of the crystal differs from the specification shown in the Crystal Characteristics table? A37: None of the parameters should be varied. We have not characterized any such crystals, and have no easy method of doing so. A crystal whose parameters deviate from the requirements may work in most applications but fail in isolated cases involving certain loop configurations or other system variations. Therefore, customers choosing to vary any of these parameters do so at their own risk. Q38: It has been noted in some other designs that the crystal has a capacitor from each pin to ground. Changing these capacitances allows the freLucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Questions and Answers (continued)
Miscellaneous (continued)
Q44: Is there a recommended method for powering the T7234? For example, is it desirable to separate the power supplies, etc.? A44: The T7234 is not extremely sensitive to powersupply schemes. Following standard practices of decoupling power supplies close to the chip and, if power and ground planes are not used, keeping power traces away from high-frequency signals, etc., should yield acceptable results. Separating the T7234 analog power supplies from the digital power supplies near the chip may yield a small improvement, and the same holds true for using power and ground planes vs. discrete traces. Note that if analog and digital power supplies are separated, the crystal power supply (VDDO) should be tied to the digital supplies (VDDD). See the SCNTI Family Reference Design Board Hardware User Manual (MN96-011ISDN), Appendix A for an example of a board layout that performs well. Q45: What are the filter characteristics of the PLL at the NT? A45: The -3 dB frequency is approximately 5 Hz, peaking is about 1.2 dB. Q46: Can the T7234 operate in the LT mode? A46: No, the T7234 is optimized for the NT side of the loop and cannot operate in the LT mode. Q47: Can you provide detailed information on the active and idle power consumption of the T7234? A47: The IDLE power of the T7234 is typically 35 mW. The IDLE power will be increased if CKOUT or the TDM highway are active. The discussion below presents accurate numbers for adding in the effects of CKOUT and the TDM highway. When considering active power measurement figures, it is important to note that the conditions under which power measurements are made are not always completely stated by 2B1Q IC vendors. For example, loop length is not typically mentioned in the context of power dissipation, yet power dissipation on a short loop is noticeably greater than on a long loop. There are two reasons for the increased power dissipation at shorter loop lengths: 1. The overall loop impedance is smaller, requiring a higher current to drive the loop.
2. The far-end transceiver is closer, requiring the near-end transceiver to sink more far-end current in order to maintain a virtual ground at its transmitter outputs. The following lab measurements provide an example of how power dissipation varies with loop length for a specific T7234 with its 15.36 MHz CKOUT output disabled (see the following table for information on CKOUT). Note that power dissipation on a 0-length loop (the worstcase loop) is about 35 mW higher than on a loop of >3 kft length--a significant difference. Thus, loop length needs to be considered when determining worst-case power numbers. Table 13. Power Dissipation Variation Loop Configuration 18 kft/26 awg 6 kft/26 awg 3 kft/26 awg 2 kft/26 awg 1 kft/26 awg 0.5 kft/26 awg 0 kft 135 load, ILOSS or LPBK active, no far-end transceiver* Power (mW) 270 270 274 277 285 293 305 278
* This is the configuration used by some IC manufacturers.
Also, in the case of the T7234, the use of the output clock CKOUT (pin 17) needs to be considered since its influence on power dissipation is significant. Some applications may make use of this clock, while others may leave it 3-stated. The power dissipation of CKOUT is shown in Table 14. Table 14. Power Dissipation of CKOUT CKOUT Frequency (MHz) 15.36 10.24 Power Due to CKOUT 40 pF Load (mW) 21.3 17.7 Power Due to CKOUT No Load (mW) 11.0 9.1
Another factor influencing power consumption is the S/T-interface data pattern. For example, when transmitting an INFO 4 pattern with all 1s data in the B and D channels, the power consumption is 25 mW lower than it is when transmitting INFO 2, because INFO 2 is worst case in terms of the amount of +0 and -0 transitions, and INFO 4 is best case if the data is all 1s. A typical number would lie about midway between these two. Lucent Technologies Inc.
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Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Questions and Answers (continued)
Miscellaneous (continued)
A47: (continued) Therefore, it is apparent that the conditions under which power is measured must be clearly specified. The methods Lucent has used to evaluate typical and worst-case power consumption are based on our commitment to provide our customers with accurate and reliable data. Measurements are performed as part of the factory test procedure using automated test equipment. Bench top tests are performed in actual T7234based systems to correlate the automated test data with an actual implementation. A conservative margin is then added to the test results for publication in our data sheets. The following table provides power-consumption data for several scenarios so that knowledgeable customers can fairly compare transceiver solutions. A baseline scenario is presented in the Case 1 column, and then adders are listed in the Cases 2--6 columns to account for the worst-case condition listed in each column so that an accurate worst-case figure can be determined based on the conditions that are present in a particular application. Note that the tests were run at 5 V, so changes in the supply voltage will change the power accordingly. Table 15. Power Consumption Variables Loop Configuration S/T State CKOUT, MHz (40 pF load) Temperature (C) Typical Power Consumption (mW) Baseline Case 1 >3 kft, 26 awg INFO 4 with all 1s data 3-stated 25 254 Case 2 0 kft* -- -- -- 35 Adders Case 3 Case 4 -- -- INFO 2 -- -- 26 -- 15.36 -- 22 Case 5 -- -- -- 85 5
* Some 2B1Q silicon vendors specify power using a configuration in which the IC is active and transmitting into a 135 termination, with no far-end transmitter attached. This configuration would cause an increase of 9 mW over the Case 1 column, instead of the 35 mW shown here. This highlights the importance of specifying measurement conditions accurately when making comparisons between chip vendors' power numbers. This is a worst-case number representing the state of the S/T-interface where the most +0/-0 transitions occur. In a real application, this will be a transient state, as INFO 4 will occur as soon as synchronization is achieved. The average power consumed during a typical INFO 4, assuming a 50% mix of 1s and 0s in the B and D channels, would be approximately half this number, or 13 mW. See the preceding table for a comparison of power dissipation with negligible capacitive loading on CKOUT. The 40 pF figure chosen here is intended to represent a worst-case condition.
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Questions and Answers (continued)
Miscellaneous (continued)
Q48: What would cause the STLED indicator to flash sporadically at an 11 Hz rate? A48: If the T7234 S/T-interface is operating over a long loop that is outside the range specified in the I.430/T1.605 standard, the T7234 may go into a state where it is constantly going in and out of synchronization. This causes it to cycle between ANSI states H7 and H8, producing STLED state changes between 1 Hz flashing and always on. When the S/T-interface loses synchronization, it takes about 96 ms before synchronization can be reacquired. This 96 ms cycle, coupled with the STLED switching from always on to 1 Hz flashing, can appear as 11 Hz or sporadic flashing, depending on how frequently S/T synchronization is being lost. Either of these states could cause potential confusion to maintenance personnel in the event that a T7234-based NT1 is connected to an S/T loop that is longer than permitted by the standards. For example, an 11 Hz rate is difficult to visually distinguish from the 8 Hz rate, but the 11 Hz case indicates a problem on the S/T-interface and the 8 Hz case indicates a problem on the U-interface. To troubleshoot the STLED indication, unplug the S/T connector and repower the T7234 and initiate a start-up on the U-interface. If there is no problem on the U-interface, the STLED will reach a 1 Hz flashing state and remain there, indicating that the fast flashing was a result of S/T-interface problems. Q49: The STLED on my T7234-based NT1 behaves in an unexpected way. When a start-up attempt is received, it flashes at an 8 Hz rate. Then it flashes briefly at 1 Hz, indicating synchronization on the U-interface. This is expected. However, after this, it starts flashing at 8 Hz, and yet it appears as though the system is operating fine (data is being passed end to end, etc.). Shouldn't the STLED signal be always low (i.e., ON) at this point?
A49: Yes it should. Referring to the STLED Control Flow diagram in Figure 10 of this data sheet, it appears as though you may be receiving aib = 0 from the upstream U-interface element. This will cause the behavior you are seeing. Q50: We are testing out T7234-based equipment against an Lucent SLC Series 5, and performance seems OK except that we get a burst of errors, and even drop calls, approximately every 15 minutes. Can you explain why? A50: Check to make sure that your equipment is setting the ps1/ps2 power status bits correctly. The SLC equipment monitors the ps1/2 bits and, if they are both zero (meaning all power is lost), it assumes that there is some sort of terminal error, since this is not an appropriate steady-state value for ps1/2. When this condition is detected, the SLC deactivates and reactivates the line approximately every 15 minutes. This causes the symptoms you describe. Q51: When I try to activate our T7234-based NT1, it appears as though the U-interface is synchronizing (i.e., STLED flashes at 1 Hz), but the S/Tinterface won't activate, and there is not even any signal activity on the S/T-interface (i.e., no INFO 1 or INFO 2). What might the problem be? A51: The behavior you have observed can be caused if the uoa bit received on the U-interface from the network is set to 0. This causes the T7234 to activate the U-interface only, keeping the S/T-interface quiet, per the ANSI and ETSI standards. We have heard of some network equipment that incorrectly sets this bit low.
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
CFR1: Act bit mode, serial interface microprocessor interrupt. Receive activation (register CFR1, bit 0). Activation/deactivation state change on U-interface (register UIR0, bit 1). Activation/deactivation state change on U-interface interrupt mask (register UIR1, bit 1). Act mode select (register GR2, bit 6). Transmit activation (register GR1, bit 4). Adaptive filter reset (register CFR0, bit 1). Alarm indication bit (register CFR1, bit 6). American National Standards Institute. Alternate space inversion. Automatic activation control (register GR0, bit 6). Auto control enable (register GR0, bit 3). Automatic eoc processor enable (register GR0, bit 4). Receive eoc address (register ECR2, bits 0--2). Transmit eoc address (register ECR0, bits 0--2). Block error on U-interface (register UIR0, bit 2). Block error on U-interface interrupt mask (register UIR1, bit 2). Corrupt cyclic redundancy check (register ECR0, bit 7). Charged-device model. Control flow state machine control--maintenance/reserved bits register. ECR2: ECR3: EMINT: EMINTM: EOC: EOCSC: EOCSCM: CFR2: CKOUT: CODEC: Control flow state machine status register. Control flow state machine status--reserved bits register. Clock output. Coder/decoder, typically used for analog-to-digital conversions or digital-to-analog conversions. CKOUT rate control (register GR0, bits 2--1). Cyclic redundancy check. Data flow control--U and S/T B-channels register. Data flow control--D-channels and TDM bus register. Receive eoc data or message indicator (register ECR2, bit 3). Transmit eoc data or message indicator (register ECR0, bit 3). Digital pair gain system. eoc state machine control--address register. eoc state machine status--address register. eoc state machine status--information register. Exit maintenance mode interrupt (register MIR0, bit 2). Exit maintenance mode interrupt mask (register MIR1, bit 2). Embedded operations channel. eoc state change on U-interface (register UIR0, bit 0). eoc state change on U-interface mask (register UIR1, bit 0).
Glossary
ACTMODE/INT: ACTR: ACTSC:
ACTSCM:
CRATE[1:0]: CRC: DFR0: DFR1: DMR: DMT: DPGS: ECR0:
ACTSEL: ACTT: AFRST: AIB: ANSI: ASI: AUTOACT: AUTOCTL: AUTOEOC: A[3:1]R: A[3:1]T: BERR: BERRM: CCRC: CDM: CFR0:
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Insertion loss test control (register CFR0, bit 0). Insertion loss test control. Integrated services digital network. International Telecommunication Union-Telecommunication Sector. Receive eoc information (register ECR3, bits 0--7). Transmit eoc information (register ERC1, bits 0--7). Line driver negative output for U-interface. Line driver positive output for U-interface. U-interface analog loopback (register GR1, bit 0). Q-channel bits register. S subchannel 1 register. S subchannel 2 register. S subchannel 3 register. S subchannel 4 register. S subchannel 5 register. Maintenance interrupt (register GIR0, bit 2). Maintenance interrupt register. Maintenance interrupt mask register. Metallic loop termination. Multiframing control (register GR0, bit 5). Near-end block error (register CFR1, bit 4). NT test mode (register GR1, bit 3). Out of frame (register CFR1, bit 2). Optoisolator input. Other U-interface state change (register UIR0, bit 3).
Glossary (continued)
ERC1: ESD: ETSI: FEBE: FSC[2:0]: FSP: FT: FTE/TDMDI: GIR0: GNDA: GNDO: GR0: GR1: GR2: HBM: HDLC: HIGHZ: HN: HP: I4C: I4CM: I4I: ILINT: ILINTM: eoc state machine control-- information register. Electrostatic discharge. European Telecommunications Standards Institute. Far-end block error (register CFR1, bit 5). Frame strobe (FS) control, (register TDR0, bits 2--0). Frame strobe (FS) polarity (register TDR0, bit 3). Fixed/adaptive timing control (register GR2, bit 0). Fixed/adaptive timing mode select. Global interrupt register. Analog ground. Crystal oscillator ground. Global device control--device configuration register. Global device control-- U-interface register. Global device control-- S/T-interface register. Human-body model. High-level data link control. High-impedance control. Hybrid negative input for U-interface. Hybrid positive input for U-interface. INFO 4 change (register SIR0, bit 3). INFO 4 change mask (register SIR1, bit 3). INFO 4 indicator (register CFR1, bit 7). Insertion loss interrupt (register MIR0, bit 1). Insertion loss interrupt mask (register MIR1, bit 1).
ILOSS: ILOSS: ISDN: ITU-T:
I[8:1]R: I[8:1]T: LON: LOP: LPBK: MCR0: MCR1: MCR2: MCR3: MCR4: MCR5: MINT: MIR0: MIR1: MLT: MULTIF: NEBE: NTM: OOF: OPTOIN: OUSC:
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
SAI[1:0]: SC1[4:1]: SC2[4:1]: SC3[4:1]: SC4[4:1]: SC5[4:1]: SCK: SDI: SDINN: SDINP: SDO: SFECV: SFECVM: SINT: SIR0: SIR1: SOM: SOMM: SPWRUD: SRESET: STLED: STOA: Superframe: S/T-interface activity indicator control (register GR1, bits 6--7). S subchannel 1 (register MCR1, bits 0--3). S subchannel 2 (register MCR2, bits 0--3). S subchannel 3 (register MCR3, bits 0--3). S subchannel 4 (register MCR4, bits 0--3). S subchannel 5 (register MCR5, bits 0--3). Serial interface clock. Serial interface data input. Sigma-delta A/D negative input for U-interface. Sigma-delta A/D positive input for U-interface. Serial interface data output. S-channel far-end code violation (register SIR0, bit 2). S-subchannel far-end code violation mask (register SIR1, bit 2). S/T-transceiver interrupt (register GIR0, bit 1). S/T-interface interrupt register. S/T-interface interrupt mask register. Start of multiframe (register SIR0, bit 0). Start of multiframe mask (register SIR1, bit 0). S/T-interface powerdown control (register GR2, bit 1). S/T-interface reset (register GR2, bit 2). Status LED driver. S/T-only activation (register GR2, bit 7). Eight U-frames grouped together.
Glossary (continued)
OUSCM: PS1: PS1E/TDMDO: PS2: PS2E/TDMCLK: QMINT: QMINTM: QSC: QSCM: Q[4:1]: R25R: R25T: R64T: RESET: RNR: RPR: RSFINT: RSFINTM: R[16:15]R: R[16:15]T: R[64:54:44:34]R: Other U-interface state change mask (register UIR1, bit 3). Power status #1 (register GR1, bit 2). Power status #1, TDM clock. Power status #2 (register GR1, bit 1). Power status #2, TDM data out. Quiet mode interrupt (register MIR0, bit 0). Quiet mode interrupt mask (register MIR1, bit 0). Q-bits state change (register SIR0, bit 1). Q-bits state change mask (register SIR1, bit 1). Q-channel bits (register MCR0, bits 0--3). Receive reserved bits (register CFR2, bit 2). Transmit reserved bit (register CFR0, bit 4). Transmit reserved bit (register CFR0, bit 5). Reset. Receive negative rail for S/T-interface. Receive positive rail for S/T-interface. Receive superframe interrupt (register UIR0, bit 4). Receive superframe interrupt mask (register UIR1, bit 4). Receive reserved bits (register CFR2, bits 1--0). Transmit reserved bits (register CFR0, bits 3--2). Receive reserved bits (register CFR2, bits 6--3).
Lucent Technologies Inc.
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T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Data Sheet February 1998
Transmit superframe interrupt mask (register UIR1, bit 5). An 18-bit synchronous word. Nontransparent 2B+D loopback control (register GR2, bit 4). Transparent 2B+D loopback control (register ECR0, bit 6). U-interface loopback of B1 channel control (register ECR0, bit 4). U-interface loopback of B2 channel control (register ECR0, bit 5). U-transceiver interrupt (register GIR0, bit 0). U-interface interrupt register. U-interface interrupt mask register. U-interface only activation, (register CFR1, bit 3). U-interface transmit path source for B1 channel (register DFR0, bits 1--0). U-interface transmit path source for B2 channel (register DFR0, bits 3--2). U-interface transmit path source for D channel (register DFR1, bit 0). Analog power. Crystal oscillator power. Common-mode voltage reference for U-interface circuits. Negative voltage reference for Uinterface circuits. Positive voltage reference for Uinterface circuits. Crystal #1. Crystal #2. U-transceiver active (register CFR1, bit 1). Transparency (register GR1, bit 5).
Glossary (continued)
SXB1[1:0]: S/T-interface transmit path source for B1 channel (register DFR0, bits 5--4). S/T-interface transmit path source for B2 channel (register DFR0, bits 7--6). S/T-interface transmit path source for D channel (register DFR1, bit 1). S/T-interface D-channel echo bit control (register GR2, bit 3).
TSFINTM: U frame: U2BDLN: U2BDLT: UB1LP: UB2LP: UINT: UIR0: UIR1: UOA: UXB1[1:0]:
SXB2[1:0]:
SXD:
SXE:
SYN8K/LBIND/FS: Synchronous 8 kHz clock or loopback indicator, frame strobe. TDM: TDMB1S: Time-division multiplexed. TDM bus transmit control for B1 channel from S/T-interface (register DFR1, bit 2). TDM bus transmit control for B1 channel from U-interface (register DFR1, bit 5). TDM bus transmit control for B2 channel from S/T-interface (register DFR1, bit 3). TDM bus transmit control for B2 channel from U-interface (register DFR1, bit 6). TDM bus transmit control for D channel from S/T-interface (register DFR1, bit 4). TDM bus transmit control for D channel from U-interface (register DFR1, bit 7). TDM bus select (register GR2, bit 5). TDM bus timing control register. Transmit negative rail for S/T-interface. Transmit positive rail for S/T-interface. Transmit superframe interrupt (register UIR0, bit 5).
TDMB1U:
TDMB2S:
UXB2[1:0]:
TDMB2U:
UXD:
TDMDS:
VDDA: VDDO: VRCM: VRN: VRP: X1: X2: XACT: XPCY:
TDMDU:
TDMEN: TDR0: TNR: TPR: TSFINT:
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Lucent Technologies Inc.
Data Sheet February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
ITU-T International Telecommunication UnionTelecommunication Sector Place des Nations CH 1211 Geneve 20, Switzerland Tel: 41-22-730-5285 FAX: 41-22-730-5991 ETSI European Telecommunications Standards Institute BP 152 F-06561 Valbonne Cedex, France Tel: 33-92-94-42-00 FAX: 33-93-65-47-16 TTC (Japan) TTC Standard Publishing Group of the Telecommunications Technology Committee 2nd Floor, Hamamatsucho-Suzuki Building, 1 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 81-3-3432-1551 FAX: 81-3-3432-1553
Standards Documentation
Telecommunication technical standards and reference documentation may be obtained from the following organizations: ANSI (U.S.A.) American National Standards Institute (ANSI) 11 West 42nd Street New York, New York 10036 Tel: 212-642-4900 FAX: 212-302-1286 Lucent Technologies Publications Lucent Technologies Customer Information Center (CIC) Tel: 800-432-6600 FAX: 800-566-9568 (in U.S.A.) FAX: 317-322-6484 (outside U.S.A.) Bellcore (U.S.A.) Bellcore Customer Service 8 Corporate Plaza Piscataway, New Jersey 08854 Tel: 800-521-CORE (in U.S.A.) Tel: 908-699-5800 FAX: 212-302-1286
Lucent Technologies Inc.
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For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell), FRANCE: (33) 1 41 45 77 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1998 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A.
February 1998 DS97-410ISDN (Replaces DS96-097ISDN)
Printed On Recycled Paper

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